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SN65HVD1040D Datasheet(PDF) 8 Page - Texas Instruments |
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SN65HVD1040D Datasheet(HTML) 8 Page - Texas Instruments |
8 / 23 page www.ti.com 50% 50% 50% NOTE: CL = 100 pF Includes Instrumentation and Fixture Capacitance Within ±20% CANH CANL C L TXD STB RXD + VO − 15 pF +20% DUT 60 W +1% TXD Input RXD Output tloop2 tloop1 VCC 0 V VOH VOL STB CANH CANL VO 500 mV 900 mV CL (see Note B) RL = 60 W +1% TXD (see Note A) VI VO tdom VCC 0 V VOD(D) 0 V VI 1.5 V CANH CANL RXD V O V I IO C L STB 3.5 V V I V O 400 mV 2.65 V 1.5 V VOH VOL (see Note A) VCC (see Note B) 0.7 ms tBUS SN65HVD1040 SLLS631B – MARCH 2007 – REVISED APRIL 2007 A. All VI input pulses are from 0 V to VCC and supplied by a generator with the following characteristics: tr or tf ≤ 6 ns. Pulse Repetition Rate (PRR) = 125 kHz, 50% duty cycle. Figure 9. tloop Test Circuit and Voltage Waveforms A. All VI input pulses are from 0 V to VCC and supplied by a generator with the following characteristics: tr or tf ≤ 6 ns. Pulse Repetition Rate (PRR) = 500 Hz, 50% duty cycle. B. CL = 100 pF includes instrumentation and fixture capacitance within 20%. Figure 10. Dominant Time-Out Test Circuit and Waveform A. For VI bit width ≤ 0.7 µs, VO = VOH. For VII bit width ≥ 5 µs, VO = VOL. VI input pulses are supplied from a generator with the following characteristics; tr or tf ≤ 6 ns. Pulse Repetition Rate (PRR) = 50 Hz, 30% duty cycle. B. CL = 15 pF includes instrumentation and fixture capacitance within 20%. Figure 11. tBUS Test Circuit and Waveform 8 Submit Documentation Feedback |
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