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SN65LVCP404 Datasheet(PDF) 4 Page - Texas Instruments |
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SN65LVCP404 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 21 page www.ti.com PACKAGE THERMAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS SN65LVCP404 SLLS700 – MARCH 2007 PACKAGE THERMAL CHARACTERISTICS(1) NOM UNIT θ JA (junction-to-ambient) 33 °C/W θ JB (junction-to-board) 20 °C/W 4-layer JEDEC Board (JESD51-7) using eight GND-vias θ-0.2 on the θ JC (junction-to-case) 23.6 °C/W center pad as shown in the section: Recommended PCB footprint with boundary and environment conditions of JEDEC Board PSI-jt (junction-to-top pseudo) 0.6 °C/W (JESD51-2) PSI-jb (junction-to-board pseudo) 19.4 °C/W θ JP (junction-to-pad) 5.4 °C/W (1) See application note SPRA953 for a detailed explanation of thermal parameters (http://www-s.ti.com/sc/psheets/spra953/spra953.pdf). over operating free-air temperature range (unless otherwise noted)(1) UNIT VCC Supply voltage range(2) –0.5 V to 6 V Control inputs, all outputs –0.5 V to (VCC + 0.5 V) Voltage range Receiver inputs –0.5 V to 4 V Human Body Model(3) All pins 3 kV ESD Charged-Device Model(4) All pins 500 V See Package Thermal Characteristics TJ Maximum junction temperature Table Moisture sensitivity level 2 Reflow temperature package soldering, 4 seconds 260 °C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. (3) Tested in accordance with JEDEC Standard 22, Test Method A114-A. (4) Tested in accordance with JEDEC Standard 22, Test Method C101. 4 Submit Documentation Feedback |
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