8

FN9206.2

January 3, 2006

This feature helps prevent a negative transient on the output

voltage when the output is shut down, eliminating the

Schottky diode that is used in some systems for protecting

the load from reversed output voltage events.

In addition, more than 400mV hysteresis also incorporates

into the three-state shutdown window to eliminate PWM

input oscillations due to the capacitive load seen by the

PWM input through the body diode of the controller’s PWM

output when the power-up and/or power-down sequence of

bias supplies of the driver and PWM controller are required.

Power-On Reset (POR) Function

During initial startup, the VCC voltage rise is monitored.

Once the rising VCC voltage exceeds 6.9V (typically),

operation of the driver is enabled and the PWM input signal

takes control of the gate drives. If VCC drops below the

falling threshold of 5.6V (typically), operation of the driver is

disabled.

Pre-POR Overvoltage Protection

Prior to VCC exceeding its POR level, the upper gate is held

low and the lower gate is controlled by the overvoltage

protection circuits during initial startup. The PHASE is

connected to the gate of the low side MOSFET (LGATE),

which provides some protection to the microprocessor if the

upper MOSFET(s) is shorted during initial start-up. For

complete protection, the low side MOSFET should have a

gate threshold well below the maximum voltage rating of the

load/microprocessor.

When VCC drops below its POR level, both gates pull low

and the Pre-POR overvoltage protection circuits are not

activated until VCC resets.

Internal Bootstrap Device

Both drivers feature an internal bootstrap schottky diode.

Simply adding an external capacitor across the BOOT and

PHASE pins completes the bootstrap circuit. The bootstrap

function is also designed to prevent the bootstrap capacitor

from overcharging due to the large negative swing at the

trailing-edge of the PHASE node. This reduces voltage

stress on the boot to phase pins.

The bootstrap capacitor must have a maximum voltage

rating above UVCC + 5V and its capacitance value can be

chosen from the following equation:

control MOSFETs per channel. The

defined as the allowable droop in the rail of the upper gate

drive.

As an example, suppose two IRLR7821 FETs are chosen as

assume a 200mV droop in drive voltage over the PWM

cycle. We find that a bootstrap capacitance of at least

0.267

µF is required.

Gate Drive Voltage Versatility

The ISL6614B provides the user flexibility in choosing the

gate drive voltage for efficiency optimization. The ISL6614B

ties the upper and lower drive rails together. Simply applying

a voltage from 5V up to 12V on PVCC sets both gate drive

rail voltages simultaneously. Connecting a SOT-23 package

type of dual schottky diodes from the VCC to BOOT1 and

BOOT2 can bypass the internal bootstrap devices of both

upper gates so that the part can operate as a dual ISL6612B

driver, which has a fixed VCC (7 to 12V typically) on the

upper gate and a programmable lower gate drive voltage.

Power Dissipation

Package power dissipation is mainly a function of the

external gate resistance, and the selected MOSFET’s

internal gate resistance and total gate charge. Calculating

the power dissipation in the driver for a desired application is

critical to ensure safe operation. Exceeding the maximum

allowable power dissipation level will push the IC beyond the

maximum recommended operating junction temperature of

125°C. The maximum allowable IC power dissipation for the

SO14 package is approximately 1W at room temperature,

while the power dissipation capacity in the QFN packages,

with an exposed heat escape pad, is around 2W. See Layout

Considerations paragraph for thermal transfer improvement

∆V

BOOT_CAP

--------------------------------------

≥

•

•

=

(EQ. 1)

50nC

20nC

FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE

VOLTAGE

1.6

1.4

1.2

1.

0.8

0.6

0.4

0.2

0.0

0.3

0.0

0.1

0.2

0.4

0.5

0.6

0.9

0.7

0.8

1.0

ISL6614B