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ISL6540CRZA Datasheet(PDF) 9 Page - Intersil Corporation |
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ISL6540CRZA Datasheet(HTML) 9 Page - Intersil Corporation |
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9 / 20 page  9 FN9214.0 March 9, 2006 Functional Pin Description VSEN+ (Pin 1) This pin provides differential remote sense for the ISL6540. It is the positive input of a standard instrumentation amplifier topology with unity gain, and should connect to the positive rail of the load/processor. The voltage at this pin should be set equal to the internal system reference voltage (0.591V typical.) VSEN- (Pin 2) This pin provides differential remote sense for the regulator. It is the negative input of the instrumentation amplifier, and should connect to the negative rail of the load/processor. Typically 50 µA is sourced from this pin. The output of the remote sense buffer is disabled (High Impedance) by pulling VSEN- to VCC. REFOUT (Pin 3) This pin connects to the unmargined system reference through an internal buffer. It has a 19mA drive capability with an output common mode range of GND to VCC. The REFOUT buffer requires at least 1 µF of capacitive loading to be stable. This pin should not be left floating. REFIN (Pin 4) When the external reference pin (REFIN) is NOT within ~800 mV of VCC, the REFIN pin is used as the system reference instead of the internal 0.591V reference. The recommended REFIN input voltage range is ~60mV to VCC - 1.8V. SS (Pin 5) This pin provides softstart functionality for the ISL6540. A capacitor connected to ground along with the internal 38mA Operational Transconductance Amplifier (OTA), sets the soft-start interval of the converter. This pin is directly connected to the non-inverting input of the Error Amplifier. To prevent noise injection into the error amplifier the SS capacitor should be located within 150 mils of the SS and GND pins. OFS+ (Pin 6) This pin sets the positive margining offset voltage. Resistors should be connected to GND (ROFS+ ) and OFS-( RMARG) from this pin. With MAR_CTRL logic low, the internal 0.591V reference is developed at the OFS+ pin across resistor ROFS+. The voltage on OFS+ is driven from OFS- through RMARG. The resulting voltage differential between OFS+ and OFS- is divided by 5 and imposed on the system reference. The maximum designed offset of 1V between OFS+ and OFS- pins translates to a 200mV offset. OFS- (Pin 7) This pin sets the negative margining offset voltage. Resistors should be connected to GND (ROFS- ) and OFS+ (RMARG) from this pin. With MAR_CTRL logic low, the internal 0.591V reference is developed at the OFS- pin across resistor ROFS-. The voltage on OFS- is driven from OFS+ through RMARG. The resulting voltage differential between OFS+ and OFS- is divided by 5 and imposed on the system reference. The maximum designed offset of -1V between OFS+ and OFS- pins translates to a -200mV offset of the system reference. VCC (Pin 8, Analog Circuit Bias) This pin provides power for the ISL6540 analog circuitry. The pin should be connected to a 2.9V to 5.6V bias through an RC filter from PVCC to prevent noise injection into the analog circuitry. This pin can be powered off the internal or external linear regulator options. MARCTRL (Pin 9) The MARCTRL pin controls margining function, a logic high enables positive margining, a logic low sets negative margining, a high impedance disables margining. PG_DLY (Pin 10) Provides the ability to delay the output of the PGOOD assertion by connecting a capacitor from this pin to GND. A 0.1µF capacitor produces approximately a 5ms delay. PGOOD (Pin 11) Provides an open drain Power Good signal when the output is within 9% of nominal output regulation point with 6% hysteresis (15%/9%), and after soft-start is complete. PGOOD monitors the VMON pin. EN (Pin 12) This pin is compared with an internal 0.49V reference and enables the soft-start cycle. This pin also can be used for voltage monitoring. A 10 µA current source to GND is active while the part is disabled, and is inactive when the part is enabled. This provides functionality for programmable hysteresis when the EN pin is used for voltage monitoring. VFF (Pin 13) The voltage at this pin is used for input voltage feed forward compensation and sets the internal oscillator ramp peak to peak amplitude at 0.16 * VFF. An external RC filter may be required at this pin in noisy input environments. The minimum recommended VFF voltage is 2.97V. VIN (Pin 14, Internal Linear Regulator Input) This pin should be tied directly to the input rail when using the internal or external linear regulator options. It provides power to the External/Internal Linear drive circuitry. When used with an external 3.3V to 5V supply, this pin should be tied directly to PVCC. ISL6540 |
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