Electronic Components Datasheet Search |
|
TLV320AIC3106IGQE Datasheet(PDF) 11 Page - Texas Instruments |
|
TLV320AIC3106IGQE Datasheet(HTML) 11 Page - Texas Instruments |
11 / 99 page www.ti.com TIMING CHARACTERISTICS (1) WCLK SDOUT BCLK SDIN td(DO-BCLK) th(WS) tL(BCLK) ts(WS) td(DO-WS) tH(BCLK) tP(BCLK) ts(DI) th(DI) TLV320AIC3106 SLAS509A – DECEMBER 2006 – REVISED APRIL 2007 All specifications typical at 25 °C, DVDD = 1.8 V IOVDD = 1.1 V IOVDD = 3.3 V PARAMETER UNIT MIN MAX MIN MAX td (WS) ADWS/WCLK delay time 50 15 ns td (DO-BCLK) BCLK to DOUT delay time 50 15 ns ts(DI) DIN setup time 10 6 ns th(DI) DIN hold time 10 6 ns tr Rise time 30 10 ns tf Fall time 30 10 ns (1) All timing specifications are measured at characterization but not tested at final test. Figure 3. I2S/LJF/RJF Timing in Slave Mode 11 Submit Documentation Feedback |
Similar Part No. - TLV320AIC3106IGQE |
|
Similar Description - TLV320AIC3106IGQE |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |