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UCD7230PWPR Datasheet(PDF) 9 Page - Texas Instruments |
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UCD7230PWPR Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 33 page  www.ti.com DEVICE INFORMATION UCD7230 SLUS741C – NOVEMBER 2006 – REVISED MARCH 2007 TERMINAL FUNCTIONS TERMINAL UCD7230 I/O DESCRIPTION NAME HTSSOP- QFN-20 20 Supply input pin to power the internal circuitry except the driver outputs. The VDD 1 18 - UCD7230 accepts an input range of 4.5 V to 15.5 V. Synchronous Rectifier Enable. The SRE pin is a high impedance digital input capable of accepting 3.3-V logic level signals, used to disable the synchronous SRE 2 19 I rectifier switch. The synchronous rectifier is disabled when this signal is low. A Schmitt trigger input comparator desensitizes this pin from external noise. The IN pin is a high impedance digital input capable of accepting 3.3-V logic IN 3 20 I level signals up to 2 MHz. A Schmitt trigger input comparator desensitizes this pin from external noise. Regulated 3.3-V rail. The onboard linear voltage regulator is capable of 3V3 4 1 O sourcing up to 10 mA of current. Bypass with 0.22- µF ceramic capacitance from this pin to analog ground, AGND. AGND 5 2 - Analog ground return. Requires a resistor to AGND for setting the current sense blanking time for both the high-side and low-side current sense comparators. The value of this DLY 6 3 I resistor in conjunction with the resistor in series with the CS+ pin sets the high side current sense threshold. Output current limit threshold set pin. The output current threshold is 1/10th of the value set on this pin. If left floating the voltage on this pin is 0.55 V. The ILIM 7 4 I voltage on the ILIM pin can range from 0.25 V to 1V to set the threshold from 25 mV to 100 mV. Current Limit Flag. The CLF signal is a 3.3-V digital output which is latched CLF 8 5 O high after an over current event, triggered by either of the two current sense comparators and reset after two rising edges received on the IN pin. Sets the current sense linear amplifier “Zero” output level. The default value is IO 9 6 I 0.6 V which allows negative current measurement. Current sense linear amplifier output. The output voltage level on this pin AO 10 7 O represents the average output current. Any value below the level on the I0 pin represents negative output current. Non-inverting input of the output current sense amplifier and current limit POS 11 8 I comparator. Inverting input of the output current sense amplifier and current limit NEG 12 9 I comparator. Power ground return. This pin should be connected close to the source of the PGND 13 10 - low-side synchronous rectifier MOSFET. The low-side high-current TrueDrive™ driver output. Drives the gate of the OUT2 14 11 I low-side synchronous MOSFET between PVDD and PGND. Supply pin provides power for the output drivers. It is not connected internally PVDD 15 12 - to the VDD supply rail. The bypass capacitor for this pin should be returned to PGND. Floating OUT1 driver supply powered by an external Schottky diode from the BST 16 13 I PVDD pin during the synchronous MOSFET on time. The high-side high-current TrueDrive™ driver output. Drives the gate of the OUT1 17 14 I high-side buck MOSFET between SW and BST. SW 18 15 I/O OUT1 gate drive return and square wave input to output inductor. CSBIAS 19 16 I Supply pin for the high-side current sense comparator. Non-inverting Input for the high side current sense comparator. A resistor CS+ 20 17 I connected between this pin and the high side MOSFET drain, in conjunction with the DLY resistor sets the high-side current limit threshold. 9 |
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