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ADSP-21065LKCA-264 Datasheet(PDF) 5 Page - Analog Devices |
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ADSP-21065LKCA-264 Datasheet(HTML) 5 Page - Analog Devices |
5 / 44 page REV. C ADSP-21065L –5– I/O transfers). Programs can be downloaded to the ADSP-21065L using DMA transfers. Asynchronous off-chip peripherals can control two DMA channels using DMA Request/Grant lines ( DMAR 1-2, DMAG1-2). Other DMA features include interrupt generation on completion of DMA transfers and DMA chaining for automatically linked DMA transfers. Serial Ports The ADSP-21065L features two synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices. The serial ports can operate at 1x clock frequency, providing each with a maximum data rate of 33 Mbit/s. Each serial port has a primary and a secondary set of transmit and receive channels. Independent transmit and receive functions provide greater flexibility for serial communications. Serial port data can be automatically transferred to and from on-chip memory via DMA. Each of the serial ports supports three operation modes: DSP serial port mode, I 2S mode (an interface commonly used by audio codecs), and TDM (Time Division Multiplex) multichannel mode. The serial ports can operate with little-endian or big-endian transmission formats, with selectable word lengths of 3 bits to 32 bits. They offer selectable synchronization and transmit modes and optional m-law or A-law companding. Serial port clocks and frame syncs can be internally or externally generated. The serial ports also include keyword and keymask features to enhance interprocessor communication. Programmable Timers and General-Purpose I/O Ports The ADSP-21065L has two independent timer blocks, each of which performs two functions—Pulsewidth Generation and Pulse Count and Capture. In Pulsewidth Generation mode, the ADSP-21065L can gener- ate a modulated waveform with an arbitrary pulsewidth within a maximum period of 71.5 secs. In Pulse Counter mode, the ADSP-21065L can measure either the high or low pulsewidth and the period of an input waveform. The ADSP-21065L also contains twelve programmable, general purpose I/O pins that can function as either input or output. As output, these pins can signal peripheral devices; as input, these pins can provide the test for conditional branching. Program Booting The internal memory of the ADSP-21065L can be booted at system power-up from an 8-bit EPROM, a host processor, or external memory. Selection of the boot source is controlled by the BMS (Boot Memory Select) and BSEL (EPROM Boot) pins. Either 8-, 16-, or 32-bit host processors can be used for booting. For details, see the descriptions of the BMS and BSEL pins in the Pin Descriptions section of this data sheet. Multiprocessing The ADSP-21065L offers powerful features tailored to multi- processing DSP systems. The unified address space allows direct interprocessor accesses of both ADSP-21065L’s IOP registers. Distributed bus arbitration logic is included on-chip for simple, glueless connection of systems containing a maximum of two ADSP-21065Ls and a host processor. Master processor changeover incurs only one cycle of overhead. Bus lock allows indivisible read-modify-write sequences for semaphores. A vector interrupt is provided for interprocessor commands. Maximum throughput for interprocessor data transfer is 132 Mbytes/sec over the external port. DEVELOPMENT TOOLS The ADSP-21065L is supported with a complete set of software and hardware development tools, including the EZ-ICE ® In- Circuit Emulator and development software. The same EZ-ICE hardware that you use for the ADSP-21060/ ADSP-21062 also fully emulates the ADSP-21065L. Both the SHARC Development Tools family and the VisualDSP ® integrated project management and debugging environment support the ADSP-21065L. The VisualDSP project management environment enables you to develop and debug an application from within a single integrated program. The SHARC Development Tools include an easy to use Assem- bler that is based on an algebraic syntax; an Assembly library/ librarian; a linker; a loader; a cycle-accurate, instruction-level simulator; a C compiler; and a C run-time library that includes DSP and mathematical functions. Debugging both C and Assembly programs with the Visual DSP debugger, you can: • View Mixed C and Assembly Code • Insert Break Points • Set Watch Points • Trace Bus Activity • Profile Program Execution • Fill and Dump Memory • Create Custom Debugger Windows The Visual IDE enables you to define and manage multiuser projects. Its dialog boxes and property pages enable you to configure and manage all of the SHARC Development Tools. This capability enables you to: • Control how the development tools process inputs and gen- erate outputs. • Maintain a one-to-one correspondence with the tool’s com- mand line switches. The EZ-ICE Emulator uses the IEEE 1149.1 JTAG test access port of the ADSP-21065L processor to monitor and control the target board processor during emulation. The EZ-ICE provides full-speed emulation, allowing inspection and modification of memory, registers, and processor stacks. Nonintrusive in-circuit emulation is assured by the use of the processor’s JTAG inter- face—the emulator does not affect target system loading or timing. In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the SHARC processor family. Hard- ware tools include SHARC PC plug-in cards multiprocessor SHARC VME boards, and daughter and modules with multiple SHARCs and additional memory. These modules are based on the SHARCPAC™ module specification. Third Party software tools include an Ada compiler, DSP libraries, operating systems, and block diagram design tools. Additional Information For detailed information on the ADSP-21065L instruction set and architecture, see the ADSP-21065L SHARC User’s Manual, Third Edition, and the ADSP-21065L SHARC Technical Reference. EZ-ICE and VisualDSP are registered trademarks of Analog Devices, Inc. SHARCPAC is a trademark of Analog Devices, Inc. |
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