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PCA9559 Datasheet(PDF) 7 Page - NXP Semiconductors |
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PCA9559 Datasheet(HTML) 7 Page - NXP Semiconductors |
7 / 11 page Philips Semiconductors Product data PCA9559 5-bit multiplexed/1-bit latched 6-bit I2C EEPROM DIP switch 2003 Jun 27 7 AC CHARACTERISTICS LIMITS SYMBOL PARAMETER MIN. TYP. MAX. UNIT MUX_IN ⇒ MUX_OUT tPLH LOW-to-HIGH transition time — 28 37 ns tPHL HIGH-to-LOW transition time — 16 21 ns Select ⇒ MUX_OUT tPLH LOW-to-HIGH transition time — 30 39 ns tPHL HIGH-to-LOW transition time — 17 22 ns OVERRIDE_N ⇒ NON-MUXED_OUT tPLH LOW-to-HIGH transition time — 34 43 ns tPHL HIGH-to-LOW transition time — 19 25 ns OVERRIDE_N ⇒ MUX_OUT tPLH LOW-to-HIGH transition time — 31 41 ns tPHL HIGH-to-LOW transition time — 21 27 ns tR Output rise time 1.0 — 3 ns/V tF Output fall time 1.0 — 3 ns/V PF Pull-up resistor for outputs 1.0 — — ns/V CL Test load capacitance on outputs — — — pF I2C-bus tSCL SCL clock frequency 10 — 400 kHz tBUF Bus free time between a STOP and a START condition 1.3 — — µs tHD:STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 600 — — ns tLOW LOW period of SCL clock 1.3 — — µs tHIGH HIGH period of SCL clock 600 — -12 ns tSU:STA Set-up time for a repeated START condition 600 — -32 ns tHD:DAT Data hold time 0 — 10 ns tSU:DAT Data set-up time 100 — -100 ns tSP Data spike time 0 — 50 ns tSU:STO Set-up time for STOP condition 600 — 10 ns tR Rise time for both SDA and SCL signals (10 - 400 pF bus) 20 — 300 ns tI Fall time for both SDA and SCL signals (10 - 400 pF bus) 20 — 300 ns CL Capacitive load for each bus line — — 400 pF TW Write cycle time1 — 15 — ms NOTE: 1. WRITE CYCLE time can only be measured indirectly during the write cycle. During this time, the device will not acknowledge its I2C Address. |
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