TLV320AIC26IRHBR datasheet(9/74 Pages) TI

Part #	TLV320AIC26IRHBR

Description	LOW POWER STEREO AUDIO CODEC WITH HEADPHONE/SPEAKER AMPLIFIER AND 12-BIT BATTERY / TEMPERATURE / AUXILIARY ADC

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Manufacturer	TI [Texas Instruments]

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TLV320AIC26

SLAS412− DECEMBER 2003

www.ti.com

9

AUDIO INTERFACE TIMING DIAGRAMS

LRCK/ADWS

BCLK

DOUT

DIN

td (WS)

td (DO−WS)

td (DO−BCLK)

ts (DI)

th (DI)

Figure 1. I2S/LJF/RJF Timing in Master Mode

TYPICAL TIMING REQUIREMENTS (FIGURE 1)

All specifications at 25

°C, DVDD = 1.8 V (1)

PARAMETER

IOVDD = 1.1 V

IOVDD = 3.3 V

UNITS

PARAMETER

MIN

MAX

MIN

MAX

UNITS

td (WS)

ADWS/LRCK delay

25

15

ns

td (DO−WS)

ADWS to DOUT delay (for LJF mode)

25

15

ns

td (DO−BCLK)

BCLK to DOUT delay

25

15

ns

ts(DI)

DIN setup

6

ns

th(DI)

DIN hold

6

ns

tr

Rise time

10

6

ns

tf

Fall time

10

6

ns

(1) These parameters are based on characterization and are not tested in production.

LRCK/ADWS

BCLK

DOUT

DIN

td (WS)

td (DO−BCLK)

ts (DI)

th (DI)

td (WS)

Figure 2. DSP Timing in Master Mode

TYPICAL TIMING REQUIREMENTS (FIGURE 2)

All specifications at 25

°C, DVDD = 1.8 V(1)

PARAMETER

IOVDD = 1.1 V

IOVDD = 3.3 V

UNITS

PARAMETER

MIN

MAX

MIN

MAX

UNITS

td (WS)

ADWS/LRCK delay

25

15

ns

td (DO−BCLK)

BCLK to DOUT delay

25

15

ns

ts(DI)

DIN setup

6

ns

th(DI)

DIN hold

6

ns

tr

Rise time

10

6

ns

tf

Fall time

10

6

ns

(1) These parameters are based on characterization and are not tested in production.

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TLV320AIC26IRHBR Datasheet(PDF) 9 Page - Texas Instruments

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