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LM26001_0609 Datasheet(PDF) 11 Page - National Semiconductor (TI) |
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LM26001_0609 Datasheet(HTML) 11 Page - National Semiconductor (TI) |
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11 / 17 page  Operation Description (Continued) Where fnom is the nominal switching frequency set by the FREQ resistor, and fsync is a square wave. If the SYNC pin is not used, it must be pulled low for normal operation. A 10k Ω pull-down resistor is recommended to protect against a missing sync signal. Although the LM26001 is designed to operate at up to 500 kHz, maximum load current may be limited at higher frequencies due to increased temperature rise. See the Thermal Considerations section. VBIAS The VBIAS pin is used to bypass the internal regulator which provides the bias voltage to the LM26001. When the VBIAS pin is connected to a voltage greater than 3V, the internal regulator automatically switches over to the VBIAS input. This reduces the current into VIN (Iq) and increases system efficiency. Using the VBIAS pin has the added benefit of reducing power dissipation within the device. For most applications where 3V < Vout < 10V, VBIAS can be connected to Vout. If not used, VBIAS should be tied to GND. If VBIAS drops below 2.7V (typical), the device automatically switches over to supply the internal bias voltage from Vin. Total device input current is the sum of Iq, gate drive current, and VBIAS current, plus some negligible current into the FB pin. Total minimum input supply current can be calculated as shown below: Where I QG is the gate drive current, calculated as: I QG =(4.6x10 -9)xf SW Total supply input current varies according to load, system efficiency, and operating frequency. To calculate minimum input current during sleep mode, use Iq _Sleep_VB, and I BIAS_SLEEP. For input current in PWM mode, use the same equation, with Iq _PWM_VB, and IBIAS_PWM. If VBIAS is connected to ground, use the same equation with the Ibias term eliminated and either I q_Sleep_VDD or Iq_PWM- _VDD . LOW VIN OPERATION AND UVLO The LM26001 is designed to remain operational during short line transients when input voltage may drop as low as 3.0V. Minimum nominal operating input voltage is 4.0V. Below this voltage, switch R DS(ON) increases, due to the lower gate drive voltage from VDD. The minimum voltage required at VDD is approximately 3.5V for normal operation within specification. VDD can also be used as a pull-up voltage for functions such as PGOOD and FPWM. Note that if VDD is used externally, the pin is not recommended for loads greater than 1 mA. If the input voltage approaches the nominal output voltage, the duty cycle is maximized to hold up the output voltage. In this mode of operation, once the duty cycle reaches its maximum, the LM26001 can skip a maximum of seven off pulses, effectively increasing the duty cycle and thus mini- mizing the dropout from input to output. Typical off-pulse skipping waveforms are shown below. UVLO is sensed at both VIN and VDD, and is activated when either voltage falls below 2.9V (typical). Although VDD is typically less than 200mV below VIN, it will not discharge through VIN. Therefore when the VIN voltage drops rapidly, VDD may remain high, especially in sleep mode. For fast line voltage transients, using a larger capacitor at the VDD pin can help to hold off a UVLO shutdown by extending the VDD discharge time. By holding up VDD, a larger cap can also reduce the R DS(ON) (and dropout voltage) in low VIN condi- tions. Alternately, under heavy loading the VDD voltage can fall several hundred mV below VIN. In this case, UVLO may be triggered by VDD even though the VIN voltage is above the UVLO threshold. When UVLO is activated the LM26001 enters a standby state in which VDD remains charged. As input voltage and VDD voltage rise above 3.9V (typical) the device will restart from softstart mode. PGOOD A power good pin, PGOOD, is available to monitor the output voltage status. The pin is internally connected to an open drain MOSFET, which remains open while the output voltage is within operating range. PGOOD goes low (low impedance to ground) when the output falls below 85% of nominal or EN is pulled low. When the output voltage returns to within 92% of nominal, as measured at the FB pin, PGOOD returns to a high state. For improved noise immunity, there is a 5us delay between the PGOOD threshold and the PGOOD pin going low. Design Information EXAMPLE CIRCUIT Figure 7 shows a complete typical application schematic. The components have been selected based on the design criteria given in the following sections. 20179429 FIGURE 6. Off-pulse Skipping Waveforms Vin = 3.5V, Vnom = 3.3V, fnom = 305kHz www.national.com 11 |
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