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MCZ33742EGR2 Datasheet(PDF) 5 Page - Freescale Semiconductor, Inc |
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MCZ33742EGR2 Datasheet(HTML) 5 Page - Freescale Semiconductor, Inc |
5 / 65 page Analog Integrated Circuit Device Data Freescale Semiconductor 5 33742 PIN CONNECTIONS Figure 4. 33742 48-Pin Connections Table 3. 33742 48-Pin Definitions A functional description of each pin can be found in the Functional Pin description section beginning on page 22. Pin Pin Name Formal Name Definition 1, 12-16, 21-25, 36-40, 45-48 NC No Connect No connection. 2 SCLK Serial Data Clock Clock input pin for the Serial Peripheral Interface (SPI). 3 MISO Master In Slave Out SPI data sent to the MCU by the 33742. When CS is HIGH, the pin is in the high- impedance state. 4 MOSI Master Out Slave In SPI data received by the 33742. 5 CS Chip Select (Active LOW) The CS input pin is used with the SPI bus to select the 33742. When the CS is asserted LOW, the 33742 is the selected device of the SPI bus. 6 WDOG Watchdog Output (Active LOW) The WDOG output pin is asserted LOW if the software watchdog is not correctly triggered. 7 RXD Receive Data CAN bus receive data output pin. 8 TXD Transmit Data CAN bus transmit data input pin. 9 VDD Voltage Digital Drain 5.0 V regulator output pin. Supply pin for the MCU. 10 RST Reset Output (Active LOW) This is the device reset output pin whose main function is to reset the MCU. This pin has an internal pullup current source to VDD. 11 INT Interrupt Output (Active LOW) This output is asserted LOW when an enabled interrupt condition occurs. The output is a push-pull structure. 17-20 41-44 GND Ground These device ground pins are internally connected to the package lead frame to provide a 33742-to-PCB thermal path. SCLK 4 5 6 7 8 9 10 11 12 2 3 32 29 28 27 26 31 30 1 36 35 RXD 34 33 25 L3 L2 L1 L0 NC VDD TXD V2 CTRL CANH CANL NC MISO MOSI WDOG INT HS VSUP CS RST NC V2 NC |
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