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AD9868 Datasheet(PDF) 7 Page - Analog Devices |
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AD9868 Datasheet(HTML) 7 Page - Analog Devices |
7 / 36 page AD9868 Rev. 0 | Page 7 of 36 DIGITAL SPECIFICATIONS AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, RSET = 2 kΩ, unless otherwise noted. Table 4. Parameter Temp Test Level1 Min Typ Max Unit CMOS LOGIC INPUTS High Level Input Voltage Full VI DRVDD − 0.7 V Low Level Input Voltage Full VI 0.4 V Input Leakage Current 12 μA Input Capacitance Full VI 3 pF CMOS LOGIC OUTPUTS (CLOAD = 5 pF) High Level Output Voltage (IOH = 1 mA) Full VI DRVDD − 0.7 V Low Level Output Voltage (IOH = 1 mA) Full VI 0.4 V Output Rise/Fall Time High Strength Mode and CLOAD = 15 pF Full VI 1.5/2.3 ns Low Strength Mode and CLOAD = 15 pF Full VI 1.9/2.7 ns High Strength Mode and CLOAD = 5 pF Full VI 0.7/0.7 ns Low Strength Mode and CLOAD = 5 pF Full VI 1.0/1.0 ns RESET Minimum Low Pulse Width (Relative to fADC) 1 Clock cycles 1 See the Explanation of Test Levels section. SERIAL PORT TIMING SPECIFICATIONS AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted. Table 5. Parameter Temp Test Level1 Min Typ Max Unit WRITE OPERATION (See Figure 5) SCLK Clock Rate (fSCLK) Full IV 32 MHz SCLK Clock High (tHI) Full IV 14 ns SCLK Clock Low (tLOW) Full IV 14 ns SDIO to SCLK Setup Time (tDS) Full IV 14 ns SCLK to SDIO Hold Time (tDH) Full IV 0 ns SEN to SCLK Setup Time (tS) Full IV 14 ns SCLK to SEN Hold Time (tH) Full IV 0 ns READ OPERATION (See Figure 6 and Figure 7) SCLK Clock Rate (fSCLK) Full IV 32 MHz SCLK Clock High (tHI) Full IV 14 ns SCLK Clock Low (tLOW) Full IV 14 ns SDIO to SCLK Setup Time (tDS) Full IV 14 ns SCLK to SDIO Hold Time (tDH) Full IV 0 ns SCLK to SDIO (or SDO) Data Valid Time (tDV) Full IV 14 ns SEN to SDIO Output Valid to High-Z (tEZ) Full IV 2 ns 1 See the Explanation of Test Levels section. |
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