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TMS470R1B512 Datasheet(PDF) 1 Page - Analog Devices |
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TMS470R1B512 Datasheet(HTML) 1 Page - Analog Devices |
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1 / 49 page  www.ti.com FEATURES TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 • External Clock Prescale (ECP) Module • High-Performance Static CMOS Technology – Programmable Low-Frequency External Clock (CLK) • TMS470R1x 16/32-Bit RISC Core (ARM7TDMI™) • Seven Communication Interfaces: – 24-MHz System Clock (60-MHz Pipeline – Three Serial Peripheral Interfaces (SPIs) Mode) • 255 Programmable Baud Rates – Independent 16/32-Bit Instruction Set – Two Serial Communications Interfaces – Open Architecture With Third-Party Support (SCIs) – Built-In Debug Module • 224 Selectable Baud Rates – Utilizes Big-Endian Format • Asynchronous/Isosynchronous Modes • Integrated Memory • Two High-End CAN Controllers (HECCs) – 512K-Byte Program Flash • 32-Mailbox Capacity Each • 2 Banks With 14 Contiguous Sectors • Fully Compliant With CAN Protocol, Version 2.0B • Internal State Machine for Programming and Erase • High-End Timer (HET) – 32K-Byte Static RAM (SRAM) – 32 Programmable I/O Channels: • 27 Dedicated General-Purpose Input/Output • 24 High-Resolution Pins (GIO) Pins, 1 Input-Only GIO Pin, and 59 • 8 Standard-Resolution Pins Additional Peripheral I/Os – High-Resolution Share Feature (XOR) • Operating Features – High-End Timer RAM – Core Supply Voltage (VCC): 1.81 V – 2.05 V • 128-Instruction Capacity – I/O Supply Voltage (VCCIO): 3.0 V – 3.6 V • 16-Channel 10-Bit Multi-Buffered ADC – Low-Power Modes: STANDBY and HALT (MibADC) – Extended Industrial Temperature Range – 128-Word FIFO Buffer • 470+ System Module – Single- or Continuous-Conversion Modes – 32-Bit Address Space Decoding – 1.55 µs Minimum Sample and Conversion – Bus Supervision for Memory and Time Peripherals – Calibration Mode and Self-Test Features – Analog Watchdog (AWD) Timer • Eight External Interrupts – Real-Time Interrupt (RTI) • Flexible Interrupt Handling – System Integrity and Failure Detection • On-Chip Scan-Base Emulation Logic, IEEE – Interrupt Expansion Module (IEM) Standard 1149.1(1) (JTAG) Test-Access Port • Direct Memory Access (DMA) Controller • 144-Pin Plastic Low-Profile Quad Flatpack (PGE Suffix) – 32 Control Packets and 16 Channels (1) The test-access port is compatible with the IEEE Standard • Zero-Pin Phase-Locked Loop (ZPLL)-Based 1149.1-1990, IEEE Standard Test-Access Port and Boundary Clock Module With Prescaler Scan Architecture specification. Boundary scan is not – Multiply-by-4 or -8 Internal ZPLL Option supported on this device. – ZPLL Bypass Mode Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. ARM7TDMI is a trademark of Advanced RISC Machines Limited (ARM). All other trademarks are the property of their respective owners. ADVANCE INFORMATION concerns new products in the sampling Copyright © 2005–2006, Texas Instruments Incorporated or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. |
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