TPS3610U18, TPS3610T50

BATTERY BACKUP SUPERVISORS FOR RAM RETENTION

SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002

7

POST OFFICE BOX 655303

detailed description (continued)

chip-enable signal gating

The internal gating of chip-enable signals, CE, prevents erroneous data from corrupting CMOS RAM during an

undervoltage condition. The TPS3610 use a series transmission gate from CEIN to CEOUT. During normal

operation (reset not asserted), the CE transmission gate is enabled and passes all CE transitions. When reset

is asserted, this path becomes disabled, preventing erroneous data from corrupting the CMOS RAM. The short

CE propagation delay from CEIN to CEOUT enables TPS3610 devices to be used with most processors.

The CE transmission gate is disabled and CEIN is high-impedance (disable mode) while reset is asserted.

and CEIN immediately becomes high impedance if the voltage at CEIN is high. If CEIN is low while reset is

asserted, the CE transmission gate is disabled at the same time CEIN goes high, or 15

µs after RESET asserts,

whichever occurs first. This allows the current write cycle to complete during power-down. When the CE

transmission gate is enabled, the impedance of CEIN appears as a resistor in series with the load at CEOUT.

impedance of the device connected to CEIN and the load at CEOUT. To achieve minimum propagation delay,

the capacitive load at CEOUT should be minimized, and a low-output-impedance driver should be used.

turns off when the transmission gate is enabled.

15

µs

CEIN

CEOUT

RESET

t

t

t

Figure 2. Chip-Enable Timing