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AVAILABLE OPTIONS

ABSOLUTE MAXIMUM RATINGS

DISSIPATION RATING TABLE

(1)

TPS2375-1

TPS2377-1

SLVS570 – MARCH 2005

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated

circuits be handled with appropriate precautions. Failure to observe proper handling and installation

procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision

integrated circuits may be more susceptible to damage because very small parametric changes could

cause the device not to meet its published specifications.

UVLO THRESHOLDS (NOMINAL)

MARKING

TYPE

LOW

HIGH

SO-8

TSSOP-8

802.3af

30.5 V

39.3 V

--

TPS2375PW-1

2375-1

-40

°C to 85°C

Legacy

30.5 V

35.1 V

TPS2377D-1

--

2377-1

(1)

Add an R suffix to the device type for tape and reel.

(VSS)

TPS237x

-0.3 V to 100 V

Voltage

ILIM, UVLO

-0.3 V to 10 V

CLASS

-0.3 V to 12 V

0 to 515 mA

Current, sinking

PG

0 to 5 mA

DET

0 to 1 mA

CLASS

0 to 50 mA

Current, sourcing

ILIM

0 to 1 mA

Human body model

2 kV

ESD

Charged device model

500 V

8/15 kV

Maximum junction temperature range

Internally limited

Storage temperature range

-65

°C to 150°C

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds - Green Packages

260

°C

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds - Nongreen

235

°C

Packages

(1)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating

conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

(2)

(3)

(4)

Surges applied to RJ-45 of Figure 1 between pins of RJ-45, and between pins and output voltage rails per EN61000-4-2, 1999.

POWER RATING

θ

θ

°C/W

°C/W

(mW)

D (SO-8)

238

150

266

PW (TSSOP-8)

258.5

159

251

(1)

Tested per JEDEC JESD51. High-K is a (2 signal – 2 plane) test board and low-K is a double-sided

board with minimum pad area and natural convection.

(2)

For the most current package and ordering information, see the Package Option Addendum at the

end of this document, or see the TI Web site at www.ti.com.

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