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TLC2933AIPW Datasheet(PDF) 1 Page - Texas Instruments |
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TLC2933AIPW Datasheet(HTML) 1 Page - Texas Instruments |
1 / 19 page TLC2933A HIGH PERFORMANCE PHASE LOCKED LOOP SLES149 − OCTOBER 2005 1 TI.COM D VCO (Voltage-Controlled Oscillator): − Complete Oscillator Using Only One External Bias Resistor (RBIAS) − Lock Frequency: 30 MHz to 55 MHz (VDD = 3 V +5%, TA = –205C to 755C, x1 Output) 30 MHz to 60 MHz (VDD = 3.3 V +5%, TA = –205C to 755C, x1 Output) 43 MHz to 110 MHz (VDD = 5 V +5%, TA = –205C to 755C, x1 Output) − Selectable Output Frequency D PFD (Phase Frequency Detector): High Speed, Edge-Triggered Detector with Internal Charge Pump D Independent VCO, PFD Power-Down Mode D Thin Small-Outline Package (14 Terminal) D CMOS Technology D Pin Compatible TLC2933IPW description The TLC2933A is designed for phase-locked loop (PLL) systems and is composed of a voltage-controlled oscillator (VCO) and an edge-triggered type phase frequency detector (PFD). The oscillation frequency range of the VCO is set by an external bias resistor (RBIAS). The VCO has a 1/2 frequency divider at the output stage. The high speed PFD with internal charge pump detects the phase difference between the reference frequency input and signal frequency input from the external counter. Both the VCO and the PFD have inhibit functions, which can be used as power-down mode. Due to the TLC2933A high speed and stable oscillation capability, the TLC2933A is suitable for use as a high-performance PLL. AVAILABLE OPTIONS TA PACKAGE TA SMALL OUTLINE (PW) –20 °C to 75°C TLC2933AIPW PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 1 2 3 4 5 6 7 14 13 12 11 10 9 8 LOGIC VDD SELECT VCO OUT FIN −A FIN −B PFD OUT LOGIC GND VCO VDD RBIAS VCO IN VCO GND VCO INHIBIT PFD INHIBIT TEST 14-PIN TSOP (PW PACKAGE) (TOP VIEW) Copyright 2005, Texas Instruments Incorporated |
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