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ADS7807UE4 Datasheet(PDF) 8 Page - Burr-Brown (TI) |
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ADS7807UE4 Datasheet(HTML) 8 Page - Burr-Brown (TI) |
8 / 24 page ADS7807 8 SBAS022C www.ti.com HEX HEX BINARY CODE CODE BINARY CODE CODE +Full-Scale (FS – 1LSB) 9.999695V 4.999924V 3.999939V 0111 1111 1111 1111 7FFF 1111 1111 1111 1111 FFFF Midscale 0V 2.5V 2V 0000 0000 0000 0000 0000 1000 0000 0000 0000 8000 One LSB Below Midscale –305 µV 2.499924V 1.999939V 1111 1111 1111 1111 FFFF 0111 1111 1111 1111 7FFF –Full-Scale –10V 0V 0V 1000 0000 0000 0000 8000 0000 0000 0000 0000 0000 CS R/C BUSY OPERATION 1 X X None. Databus is in Hi-Z state. ↓ 0 1 Initiates conversion ‘n’. Databus remains in Hi-Z state. 0 ↓ 1 Initiates conversion ‘n’. Databus enters Hi-Z state. 01 ↑ Conversion ‘n’ completed. Valid data from conversion ‘n’ on the databus. ↓ 1 1 Enables databus with valid data from conversion ‘n’. ↓ 1 0 Enables databus with valid data from conversion ‘n – 1’(1). Conversion n in progress. 0 ↑ 0 Enables databus with valid data from conversion ‘n – 1’(1). Conversion ‘n’ in progress. 00 ↑ New conversion initiated without acquisition of a new signal. Data will be invalid. CS and/or R/C must be HIGH when BUSY goes HIGH. X X 0 New convert commands ignored. Conversion ‘n’ in progress. NOTE: (1) See Figures 2 and 3 for constraints on data valid from conversion ‘n – 1’. The ADS7807 will begin tracking the input signal at the end of the conversion. Allowing 25 µs between convert com- mands assures accurate acquisition of a new signal. Refer to Tables II and III for a summary of CS , R/C, and BUSY states, and Figures 2 through 6 for timing diagrams. CS and R/C are internally OR’ed and level triggered. There is not a requirement which input goes LOW first when initiating a conversion. If, however, it is critical that CS or R/C initiates conversion ‘n’, be sure the less critical input is LOW at least 10ns prior to the initiating input. If EXT/INT (pin 8) is LOW when initiating conversion ‘n’, serial data from conver- sion ‘n – 1’ will be output on SDATA (pin 19) following the start of conversion ‘n’. See Internal Data Clock in the Read- ing Data section. To reduce the number of control pins, CS can be tied LOW using R/C to control the read and convert modes. This will have no effect when using the internal data clock in the serial output mode. The parallel output and the serial output (only when using an external data clock), however, will be affected whenever R/C goes HIGH. Refer to the Reading Data section. READING DATA The ADS7807 outputs serial or parallel data in Straight Binary (SB) or Binary Two’s Complement data output format. If SB/BTC (pin 7) is HIGH, the output will be in SB format, and if LOW, the output will be in BTC format. Refer to Table IV for ideal output codes. The parallel output can be read without affecting the internal output registers; however, reading the data through the serial port will shift the internal output registers one bit per data CS R/C BUSY EXT/INT DATACLK OPERATION ↓ 0 1 0 Output Initiates conversion ‘n’. Valid data from conversion ‘n – 1’ clocked out on SDATA. 0 ↓ 1 0 Output Initiates conversion ‘n’. Valid data from conversion ‘n – 1’ clocked out on SDATA. ↓ 0 1 1 Input Initiates conversion ‘n’. Internal clock still runs conversion process. 0 ↓ 1 1 Input Initiates conversion ‘n’. Internal clock still runs conversion process. ↓ 1 1 1 Input Conversion ‘n’ completed. Valid data from conversion ‘n’ clocked out on SDATA synchronized to external data clock. ↓ 1 0 1 Input Valid data from conversion ‘n – 1’ output on SDATA synchronized to external data clock. Conversion ‘n’ in progress. 0 ↑ 0 1 Input Valid data from conversion ‘n – 1’ output on SDATA synchronized to external data clock. Conversion ‘n’ in progress. 00 ↑ X X New conversion initiated without acquisition of a new signal. Data will be invalid. CS and/or R/C must be HIGH when BUSY goes HIGH. X X 0 X X New convert commands ignored. Conversion ‘n’ in progress. NOTE: (1) See Figures 4, 5, and 6 for constraints on data valid from conversion ‘n – 1’. TABLE III. Control Functions When Using Serial Output. TABLE IV. Output Codes and Ideal Input Voltages. TABLE II. Control Functions When Using Parallel Output (DATACLK tied LOW, EXT/INT tied HIGH). BINARY TWO’S COMPLEMENT STRAIGHT BINARY (SB/BTC LOW) (SB/BTC HIGH) DIGITAL OUTPUT DESCRIPTION ANALOG INPUT Full-Scale Range ±10 0V to 5V 0V to 4V Least Significant Bit (LSB) 305 µV76µV61µV |
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