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TB6560HQ Datasheet(PDF) 5 Page - Toshiba Semiconductor |
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TB6560HQ Datasheet(HTML) 5 Page - Toshiba Semiconductor |
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5 / 31 page  TB6560HQ/FG 2006-05-31 5 Electrical Characteristics (Ta = 25°C, VDD = 5 V, VM = 24 V) Characteristic Symbol Test Circuit Test Condition Min Typ. Max Unit High VIN (H) 2.0 ⎯ VDD Input voltage Low VIN (L) 1 −0.2 ⎯ 0.8 V Input hysteresis voltage VH 1 M1, M2, CW/CCW, CLK, RESET , ENABLE, DECAY, TQ1, TQ2, ISD ⎯ 400 ⎯ mV IIN (H) M1, M2, CW/CCW, CLK, RESET , ENABLE, DECAY, TQ1, TQ2, ISD VIN = 5.0 V Built-in pull-down resistor 30 55 80 Input current IIN (L) 1 VIN = 0 V ⎯ ⎯ 1 µA IDD1 Output open, RESET : H, ENABLE: H (2, 1-2 phase excitation) ⎯ 3 5 IDD2 Output open, RESET : H, ENABLE: H (W1−2, 2W1-2 phase excitation) ⎯ 3 5 IDD3 RESET : L, ENABLE: L ⎯ 2 5 Consumption current VDD pin IDD4 1 RESET : H, ENABLE: L ⎯ 2 5 mA IM1 RESET : H/L, ENABLE: L ⎯ 0.5 1 Consumption current VM pin IM2 1 RESET : H/L, ENABLE: H ⎯ 0.7 2 mA Output channel margin of error ∆VO ⎯ B/A, COSC = 0.0033 µF −5 ⎯ 5 % VNFHH TQ1 = H, TQ2 = H 10 20 30 VNFHL TQ1 = L, TQ2 = H 47 50 55 VNFLH TQ1 = H, TQ2 = L 70 75 80 VNF level Level differential VNFLL ⎯ TQ1 = L, TQ2 = L 100 % Minimum clock pulse width tW (CLK) ⎯ ⎯ ⎯ 100 ⎯ ns MO output residual voltage VOL MO ⎯ IOL = 1 mA ⎯ ⎯ 0.5 V TSD TSD ⎯ (Design target value) ⎯ 170 ⎯ °C TSD hysteresis TSDhys ⎯ (Design target value) ⎯ 20 ⎯ °C Oscillating frequency fOSC C = 330 pF 60 130 200 kHz |
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