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SN65HVD22D Datasheet(PDF) 6 Page - Texas Instruments |
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SN65HVD22D Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 28 page  SN65HVD20,SN65HVD21 SN65HVD22,SN65HVD23,SN65HVD24 SLLS552D − DECEMBER 2002 − REVISED APRIL 2005 www.ti.com 6 RECEIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT VIT(+) Positive-going differential input voltage threshold See Figure 10 VO = 2.4 V, IO = −8 mA 60 200 mV VIT(−) Negative-going differential input voltage threshold See Figure 10 VO = 0.4 V, IO = 8 mA −200 −60 mV VHYS Hysteresis voltage (VIT+ − VIT−) 100 130 mV VIT(F+) Positive-going differential input failsafe voltage See Figure 15 VCM = −7 V to 12 V 40 120 200 mV VIT(F+) Positive-going differential input failsafe voltage threshold See Figure 15 VCM = −20 V to 25 V 120 250 mV VIT(F−) Negative-going differential input failsafe voltage See Figure 15 VCM = −7 V to 12 V −200 −120 −40 mV VIT(F−) Negative-going differential input failsafe voltage threshold See Figure 15 VCM = −20 V to 25 V −250 −120 mV VIK Input clamp voltage II = −18 mA −1.5 V VOH High-level output voltage VID = 200 mV, IOH = −8 mA, See Figure 11 4 V VOL Low-level output voltage VID = −200 mV, IOL = 8 mA, See Figure 11 0.4 V VI = −7 to 12 V, HVD20, HVD23 −400 500 II(BUS) Bus input current (power on or power off) VI = −7 to 12 V, Other input = 0 V HVD21, HVD22, HVD24 −100 125 µA II(BUS) Bus input current (power on or power off) VI = −20 to 25 V, HVD20, HVD23 −800 1000 µA VI = −20 to 25 V, Other input = 0 V HVD21, HVD22, HVD24 −200 250 II Input current RE −100 100 µA RI Input resistance HVD20, 23 24 k Ω RI Input resistance HVD21, 22, 24 96 k Ω CID Differential input capacitance VID = 0.5 + 0.4 sine (2π x 1.5 x 106t) 20 pF (1) All typical values are at 25°C. RECEIVER SWITCHING CHARACTERISTICS over recommended operating conditions PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH Propagation delay time, low-to-high level output See Figure 11 HVD20, HVD23 16 35 ns tPHL Propagation delay time, high-to-low level output See Figure 11 HVD21, HVD22, HVD24 25 50 ns tPHL Propagation delay time, high-to-low level output See Figure 11 HVD21, HVD22, HVD24 25 50 ns tr Receiver output rise time See Figure 11 2 4 ns tf Receiver output fall time See Figure 11 2 4 ns tPZH Receiver output enable time to high level See Figure 12 90 120 ns tPHZ Receiver output disable time from high level See Figure 12 16 35 ns tPZL Receiver output enable time to low level See Figure 13 90 120 ns tPLZ Receiver output disable time from low level See Figure 13 16 35 ns tr(standby) Time from an active receiver output to standby 2 tr(wake) Wake-up time from standby to an active receiver output See Figure 14, DE at 0 V 8 µs tsk(p) Pulse skew | tPLH – tPHL | 5 ns tsk(p) Pulse skew | tPLH – tPHL | 5 ns tsk(p) Pulse skew | tPLH – tPHL | 5 ns tp(set) Delay time, bus fail to failsafe set See Figure 15, pulse rate = 1 kHz 250 350 µs tp(reset) Delay time, bus recovery to failsafe reset See Figure 15, pulse rate = 1 kHz 50 ns |
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Similar Description - SN65HVD22D |
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