Rev0.1 Nov 30, 2005
P.2/
CP80S54/S56
GENERAL DESCRIPTION
The
CP80S54/S56 series is a family of low-cost, high speed, high noise immunity, EPROM/ROM-based 8-bit CMOS
microcontrollers. It employs a RISC architecture with only 42 instructions. All instructions are single cycle except
for program branches which take two cycles. The easy to use and easy to remember instruction set reduces
development time significantly.
The
CP80S54/S56 series consists of Power-on Reset (POR), Brown-out Reset (BOR), Power-up Reset Timer
(PWRT), Oscillator Start-up Timer(OST), Watchdog Timer, EPROM/ROM, SRAM, tri-state I/O port, I/O
pull-high/open-drain/pull-down control, Power saving SLEEP mode, real time programmable clock/counter,
Interrupt, Wake-up from SLEEP mode, and Code Protection for EPROM products. There are three oscillator
configurations to choose from, including the power-saving LP (Low Power) oscillator and cost saving RC oscillator.
The
CP80S54/S54E address 512×13 of program memory, and the CP80S56/S56E address 1K×13 of program
memory.
The
CP80S54/S56 can directly or indirectly address its register files and data memory. All special function registers
including the program counter are mapped in the data memory.
BLOCK DIAGRAM
ALU
Watchdog
Timer
Oscillator
Circuit
Timer0
PORTA
PORTB
Program
Counter
5-level
STACK
EPROM
/ ROM
SRAM
Instruction
Decoder
Accumulator
FSR
Interrupt
Control
CP
80S54/56
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