Integrated Silicon Solution, Inc. — 1-800-379-4774

7

Rev. C

11/01/01

1

2

3

4

5

6

7

8

9

10

11

12

IS61LV25616

-10

-12

-15

Symbol

Parameter

Min. Max.

Min. Max.

Min. Max.

Unit

Write Cycle Time

10

—

12

—

15

—

ns

CE to Write End

8

—

8

—

10

—

ns

Address Setup Time

8

—

8

—

10

—

ns

to Write End

Address Hold from Write End

0

—

0

—

0

—

ns

Address Setup Time

0

—

0

—

0

—

ns

LB, UB Valid to End of Write

8

—

8

—

10

—

ns

WE Pulse Width

8

—

8

—

10

—

ns

WE Pulse Width (OE = LOW)

10

—

12

—

12

—

ns

Data Setup to Write End

6

—

6

—

7

—

ns

Data Hold from Write End

0

—

0

—

0

—

ns

WE LOW to High-Z Output

—

5

—

6

—

7ns

WE HIGH to Low-Z Output

2

—

2

—

2

—

ns

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and

output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

3. The internal write time is defined by the overlap of

CE LOW and UB or LB, and WE LOW. All signals must be in valid states to

initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the

rising or falling edge of the signal that terminates the write.

Shaded area product in development