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56852 Datasheet(PDF) 10 Page - Freescale Semiconductor, Inc |
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56852 Datasheet(HTML) 10 Page - Freescale Semiconductor, Inc |
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10 / 48 page  56852 Technical Data, Rev. 8 10 Freescale Semiconductor E4 A0 Output(Z) Address Bus (A0–A16)—These pins specify a word address for external program or data memory addresses. F2 A1 F3 A2 F4 A3 F1 A4 G3 A5 G2 A6 J1 A7 H2 A8 H3 A9 J2 A10 H4 A11 G4 A12 J3 A13 F5 A14 H5 A15 E5 A16 F6 A17 TIO0 Output(Z) Input/Output Address Bus (A17) Timer I/O (0)—Can be programmed as either a timer input source or as a timer output flag. G5 A18 TIO1 Output(Z) Input/Output Address Bus (A18) Timer I/O (1)—Can be programmed as either a timer input source or as a timer output flag. H6 A19 CS3 Output(Z) Output Address Bus (A19) External Chip Select 3 —When enabled, a CSx signal is asserted for external memory accesses that fall within a programmable address range. J8 CLKO A20 Output Output Output clock (CLKO)—User programmable clock out reference Address Bus—A20 D2 CS0 GPIOA0 Output Input/Output Chip Select 0 (CS0) —When enabled, a CSx signal is asserted for external memory accesses that fall within a programmable address range. Port A GPIO (0) —A general purpose IO pin. Table 3-1. 56852 Signal and Package Information for the 81-pin MAPBGA (Continued) Pin No. Signal Name Type Description |
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