MC68HC05J5ADW datasheet(4/106 Pages) FREESCALE

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MC68HC05J5ADW Datasheet(PDF) 4 Page - Freescale Semiconductor, Inc

Part #	MC68HC05J5ADW

Description	8-bit microcontroller units

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Manufacturer	FREESCALE [Freescale Semiconductor, Inc]

Direct Link	http://www.freescale.com

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GENERAL RELEASE SPECIFICATION

July 16, 1999

MC68HC05J5A

REV 2.1

TABLE OF CONTENTS

Section

Page

4.5.2

OPTIONAL EXTERNAL INTERRUPTS (PA0-PA3) .................................... 4-6

4.5.3

TIMER INTERRUPT (MFT) ......................................................................... 4-7

4.5.4

TIMER1 INTERRUPT (16-BIT TIMER)........................................................ 4-7

SECTION 5

RESETS

5.1

EXTERNAL RESET (RESET).......................................................................... 5-2

5.2

INTERNAL RESETS ........................................................................................ 5-2

5.2.1

POWER-ON RESET (POR) ........................................................................ 5-2

5.2.2

COMPUTER OPERATING PROPERLY RESET (COPR)........................... 5-2

5.2.3

LOW VOLTAGE RESET (LVR) ................................................................... 5-3

5.2.4

ILLEGAL ADDRESS RESET (ILADR)......................................................... 5-3

SECTION 6

LOW POWER MODES

6.1

STOP INSTRUCTION...................................................................................... 6-2

6.1.1

STOP Mode ................................................................................................. 6-3

6.1.2

HALT Mode.................................................................................................. 6-3

6.2

WAIT INSTRUCTION....................................................................................... 6-4

6.3

DATA-RETENTION MODE.............................................................................. 6-4

6.4

COP WATCHDOG TIMER CONSIDERATIONS ............................................. 6-4

SECTION 7

INPUT/OUTPUT PORTS

7.1

SLOW OUTPUT FALLING-EDGE TRANSITION............................................. 7-1

7.2

PORT A............................................................................................................ 7-1

7.2.1

Port A Data Register.................................................................................... 7-2

7.2.2

Port A Data Direction Register..................................................................... 7-2

7.2.3

Port A Pulldown/up Register........................................................................ 7-3

7.2.4

Port A Drive Capability................................................................................. 7-3

7.2.5

Port A I/O Pin Interrupts............................................................................... 7-3

7.3

PORT B............................................................................................................ 7-4

7.3.1

Port B Data Register.................................................................................... 7-4

7.3.2

Port B Data Direction Register..................................................................... 7-5

7.3.3

Port B Pulldown/up Register........................................................................ 7-5

7.4

I/O PORT PROGRAMMING ............................................................................ 7-6

7.4.1

Pin Data Direction........................................................................................ 7-6

7.4.2

Output Pin.................................................................................................... 7-6

7.4.3

Input Pin....................................................................................................... 7-6

7.4.4

I/O Pin Transitions ....................................................................................... 7-7

7.4.5

I/O Pin Truth Tables..................................................................................... 7-7

Freescale Semiconductor, Inc.

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