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TMS470R1VC3382APZ-T Datasheet(PDF) 6 Page - Texas Instruments |
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TMS470R1VC3382APZ-T Datasheet(HTML) 6 Page - Texas Instruments |
6 / 55 page TMS470R1VC338, TMS470R1VC348, TMS470R1VC3382, TMS470R1VC3482 16/32-BIT RISC ROM MICROCONTROLLERS SPNS085C – JULY 2003 – REVISED JANUARY 2006 6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443 device characteristics (continued) Table 1. Device Characteristics CHARACTERIS- TICS DEVICE DESCRIPTION TMS470R1VC338/ VC3382 DEVICE DESCRIPTION TMS470R1VC348/ VC3482 COMMENTS FOR VC3X8X MEMORY For the number of memory selects on this device, see the Memory Selection Assignment table (Table 2). INTERNAL MEMORY 256K-Byte ROM 10K-Byte SRAM (VC338) 12K-Byte SRAM (VC3382) 256K-Byte ROM 10K-Byte SRAM (VC348) 12K-Byte SRAM (VC3482) ROM is pipeline-capable The VC3x8 RAM is implemented in one 10K array selected by two memory-select signals. The VC3x82 RAM is implemented in one 12K array selected by two memory-select signals. (See the Memory Selection Assignment table, Table 2). PERIPHERALS For the device-specific interrupt priority configurations, see the Interrupt Priority table (Table 4). And for the 1K peripheral address ranges and their peripheral selects, see the Peripherals and System Module Base Addresses table (Table 3). CLOCK ZPLL ZPLL Zero-pin PLL has no external loop filter pins. GENERAL- PURPOSE I/Os 5 I/O 1 Input only 11 I/O 1 Input only Port A has six (6) external pins (VC338/VC3382 – GIOA[2]/INT2 and GIOA[3]/INT3 are not available.) Port A has eight (8) external pins and Port B has four (4) external pins (VC348) ECP YES YES C2SIb 1 1 SCI 1 (3-pin) 1 (2-pin) 1 (3-pin) 1 (2-pin) SCI2 has no external clock pin, only transmit/receive pins (SCI2TX and SCI2RX) CAN (HECC and/or SCC) 1 SCC 1 SCC Standard CAN controller SPI (5-pin, 4-pin or 3-pin) 1 (5-pin) 1 (4-pin) 2 (5-pin) VC338/VC3382 SPI1 (5-pin), SPI2 (4-pin) SPI2 has no chip select pin HET with XOR Share 27 I/O 16 I/O The VC3x8x devices have both the logic and registers for a full 32-I/O HET implemented, even though not all 32 pins are available externally. The high-resolution (HR) SHARE feature allows even HR pins to share the next higher odd HR pin structures. This HR sharing is independent of whether or not the odd pin is available externally. If an odd pin is available externally and shared, then the odd pin can only be used as a general-purpose I/O. For more information on HR SHARE, see the TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199). HET RAM 64-Instruction Capacity 64-Instruction Capacity MibADC 10-bit, 12-channel 64-word FIFO 10-bit, 16-channel 64-word FIFO 12-channel MibADC (VC338x), 16-channel MibADC (VC348x). Both the logic and registers for a full 16-channel MibADC are present. Capable of being "event triggered" from a user-selectable event source. CORE VOLTAGE 1.81 - 2.06 V 1.70 - 2.06 V (-40 to 85C) 1.81 - 2.06 V 1.70 - 2.06 V (-40 to 85C) The 1.70 - 2.06 V range applies when operating between -40 and 85C. I/O VOLTAGE 3.0 - 3.6 V 3.0 - 3.6 V PINS 100 100 PACKAGE PZ PZ |
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