Philips Semiconductors

Preliminary specification

MIPS

PR31500

Poseidon embedded processor

1996 Sep 24

9

PIN #

NAME AND FUNCTION

TYPE

NAME

Memory Pins (continued)

117, 118

/CARD1CSH,L

O

These pins are the Chip Select signals for PCMCIA card slot 1.

112

/CARDREG

O

This pin is the /REG signal for the PCMCIA cards.

110

/CARDIORD

O

This pin is the /IORD signal for the PCMCIA IO cards.

111

/CARDIOWR

O

This pin is the /IOWR signal for the PCMCIA IO cards.

115

/CARDDIR

O

This pin is used to provide the direction control for bi-directional data buffers used for the PCMCIA

slot(s). This signal will assert whenever /CARD2CSH or /CARD2CSL or /CARD1CSH or

/CARD1CSL is asserted and a read transaction is taking place.

105

/CARD2WAIT

I

This pin is the card wait signal from PCMCIA card slot 2.

113

/CARD1WAIT

I

This pin is the card wait signal from PCMCIA card slot 1.

Bus Arbitration Pins

167

/DREQ

I

This pin is used to request external arbitration. If the TESTSIU signal is high and the TESTSIU

function has been enabled, then once /DGRNT is asserted, external logic can initiate reads or

writes to PR31500 processor registers by driving the appropriate input signals. If the TESTSIU

signal is low or the TESTSIU function has not been enabled, then PR31500 memory transactions

are halted and certain memory signals will be tri-stated when /DGRNT is asserted in order to allow

an external master to access memory.

166

/DGRNT

O

This pin is asserted in response to /DREQ to inform the external test logic or bus master that it can

now begin to drive signals.

Clock Pins

128

SYSCLKIN

I

This pin should be connected along with SYSCLKOUT to an external crystal which is the main

PR31500 clock source.

129

SYSCLKOUT

O

This pin should be connected along with SYSCLKIN to an external crystal which is the main

PR31500 clock source.

79

C32KIN

I

This pin along with C32KOUT should be connected to a 32.768 KHz crystal.

80

C32KOUT

O

This pin along with C32KIN should be connected to a 32.768 KHz crystal.

77

BC32K

O

This pin is a buffered output of the 32.768 KHz clock.

CHI Pins

50

CHIFS

I/O

This pin is the CHI frame synchronization signal. This pin is available for use in one of two modes.

As an output, this pin allows PR31500 to be the master CHI sync source. As an input, this pin

allows an external peripheral to be the master CHI sync source and the PR31500 CHI module will

slave to this external sync.

49

CHICLK

I/O

This pin is the CHI clock signal. This pin is available for use in one of two modes. As an output,

this pin allows PR31500 to be the master CHI clock source. As an input, this pin allows an

external peripheral to be the master CHI clock source and the PR31500 CHI module will slave to

this external clock.

52

CHIDOUT

O

This pin is the CHI serial data output signal.

51

CHIDIN

I

This pin is the CHI serial data input signal.

IO Pins

46, 107,

47, 108,

56, 64,

64

IO(6:0)

I/O

These pins are general purpose input/output ports. Each port can be independently programmed

as an input or output port. Each port can generate a separate positive and negative edge interrupt.

Each port can also be independently programmed to use a 16 to 24 msec debouncer.

30, 45

MFIO(1:0)

I/O

These pins are multi-function input/output ports. Each port can be independently programmed as

an input or output port, or can be programmed for multi-function use to support vendor-dependent

test signals (for debugging purposes only). Each port can generate a separate positive and

negative edge interrupt. Note that 30 other multi-function pins are available for usage as

multi-function input/output ports. These pins are named after their respective standard/normal

function and are not listed here.

Endian Processor Pin

29

/LB endian

I

Little/Big Endian. This pin, when pulled Low at power-up, configures the PR31500 as a Little

Endian. When this pin is pulled High at power-up, it configures the PR31500 as a Big Endian

processor.