©KEMET Electronics Corporation, P.O. Box 5928, Greenville, S.C. 29606, (864) 963-6300

CERAMIC CAPACITOR ARRAY

•

Four individual capacitors inside

one 1206 monolithic structure

•

Saves board and inventory space

•

One placement instead of four - less costly

•

Easier to handle and solder than 4 smaller chips

•

Tape and reel per EIA 481-1

•

RoHS Compliant

FEATURES

W

BW

P/2

Ref

P

L

CL

BW1

T

CAPACITOR OUTLINE DRAWING

TABLE 1

EIA DIMENSIONS – MILLIMETERS (INCHES)

1632

3.2 (0.126)

± 0.2 (0.008)

1.6 (.063)

± 0.2 (.008)

0.7 - 1.35

(0.027 - 0.053)

0.40 (0.016)

± 0.2 (0.008)

0.1 - 0.5

(0.004 - 0.020)

Size

Code

Length

L

Width

W

Thickness

T (max.)

Bandwidth

BW

Bandwidth

BW1

0.8 (0.031)

± 0.1 (0.004)

Pitch

P

Notes:

1. Metric is controlling - English for reference only.

2. Pitch (P) tolerances are non-cumulative along the package.

3. Thickness (T) depends on capacitance.

END METALLIZATION

Expressed in Picofarads (pF)

First two digits represent significant figures.

Third digit specifies number of zeros. (Use 9

for 1.0 thru 9.9pF. (Example: 2.2pF = 229

CERAMIC

EIA SIZE CODE

SPECIFICATION

CAPACITANCE CODE

VOLTAGE

C - Standard

CAPACITANCE TOLERANCE

K – ±10%: M – ±20% Standard Tolerances

Contact factory for any special requirements.

C-Standard

(Tin-plated nickel barrier)

5 = 50v; 3 = 25v; 4 = 16v; 8=10v

C

1632

C

103

K

5

R

C

FAILURE RATE LEVEL

A

A- Not Applicable

TEMPERATURE CHARACTERISTIC

Designated by Capacitance

Change Over Temperature Range

G – C0G (NP0) (±30 PPM/°C)

R – X7R (±15%)

Ceramic chip array

CERAMIC ARRAY ORDERING INFORMATION

85