Philips Semiconductors

Product specification

SA571

Compandor

1997 Aug 14

5

This paper describes an inexpensive integrated circuit, the SA571

Compandor, which offers a pair of high performance gain control

circuits featuring low distortion (<0.1%), high signal-to-noise ratio

(90dB), and wide dynamic range (110dB).

CIRCUIT BACKGROUND

The SA571 Compandor was originally designed to satisfy the

requirements of the telephone system. When several telephone

channels are multiplexed onto a common line, the resulting

signal-to-noise ratio is poor and companding is used to allow a wider

dynamic range to be passed through the channel. Figure 5

graphically shows what a compandor can do for the signal-to-noise

ratio of a restricted dynamic range channel. The input level range of

+20 to -80dB is shown undergoing a 2-to-1 compression where a

2dB input level change is compressed into a 1dB output level

change by the compressor. The original 100dB of dynamic range is

thus compressed to a 50dB range for transmission through a

restricted dynamic range channel. A complementary expansion on

the receiving end restores the original signal levels and reduces the

channel noise by as much as 45dB.

The significant circuits in a compressor or expander are the rectifier

and the gain control element. The phone system requires a simple

full-wave averaging rectifier with good accuracy, since the rectifier

accuracy determines the (input) output level tracking accuracy. The

gain cell determines the distortion and noise characteristics, and the

phone system specifications here are very loose. These specs could

have been met with a simple operational transconductance

multiplier, or OTA, but the gain of an OTA is proportional to

temperature and this is very undesirable. Therefore, a linearized

transconductance multiplier was designed which is insensitive to

temperature and offers low noise and low distortion performance.

These features make the circuit useful in audio and data systems as

well as in telecommunications systems.

BASIC CIRCUIT HOOK-UP AND OPERATION

Figure 6 shows the block diagram of one half of the chip, (there are

two identical channels on the IC). The full-wave averaging rectifier

The output of the

∆G cell is a current which is fed to the summing

node of the operational amplifier. Resistors are provided to establish

circuit gain and set the output DC bias.

INPUT

LEVEL

OUTPUT

LEVEL

NOISE

+20

0dB

–40

–80

–20

0dB

–40

–80

SR00679

Figure 5. Restricted Dynamic Range Channel

The circuit is intended for use in single power supply systems, so

the internal summing nodes must be biased at some voltage above

ground. An internal band gap voltage reference provides a very

rectifier and

Figure 7 shows how the circuit is hooked up to realize an expandor.

the

∆G cell. When the input signal drops by 6dB, the gain control

current will drop by a factor of 2, and so the gain will drop 6dB. The

expansion.

Figure 8 shows the hook-up for a compressor. This is essentially an

expandor placed in the feedback loop of the op amp. The

∆G cell is

setup to provide AC feedback only, so a separate DC feedback loop

determine the DC bias at the output of the op amp. The output will

bias to:

V

R

R

4

VCC PIN 13

GND PIN 4

OUTPUT

7,10

VREF

1.8V

R4

30k

1,16

CRECT

R1

10k

2,15

RECTIN

GIN

3,14

20k

R2

20k

R3

6,11

5,12

INVIN

R3

THD TRIM

8,9

IG

∆G

SR00680

Figure 6. Chip Block Diagram (1 of 2 Channels)

–

VIN

VOUT

VREF

∆G

*CIN1

*CIN2

*CRECT

+

R3

R4

R1

R2

GAIN

+

2R

3

V

IN

(avg)

R

1

R

2

I

B

NOTE:

IB = 140µA

*EXTERNAL COMPONENTS

SR00681

Figure 7. Basic Expander

V

1

)

R

DCTOT

30k

1.8V

The output of the expander will bias up to:

V

R

3

R

4

V

REF

V

1

)

20k

30k

1.8V

+ 3.0V

The output will bias to 3.0V when the internal resistors are used.

value.