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SP6652 Datasheet(PDF) 10 Page - Sipex Corporation |
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SP6652 Datasheet(HTML) 10 Page - Sipex Corporation |
10 / 16 page 0 May25-07 RevH SP6652 1A, High Efficiency, Current Mode PWM Buck Regulator © 2007 Sipex Corporation APPLICATIONS INFORMATION Figure 4. Typical SP6652 circuit layout. over frequency fzero = 80kHz (from the Bode plot) divided by the loop gain band- width, given as 20kHz, which is used in the following equation: Error Amp Gain = fzero / (loop gain bandwidth) = 80kHz / 20kHz = 4 The error amp transconductance is about 1mS, so this sets the RZ resistor to be: Rz = 4/1mS = 4KΩ We will use RZ = 4KΩ for the 3.3V output compensation. The zero for loop compensation is placed at the first modulator pole of 4 kHz to pro- vide a loop response of -20/dB/decade at the crossover frequency. The compensa- tion capacitor Cc can be calculated from the crossover frequency pole1 and the RZ value: CC = 1/(2π• RZ •pole1) = 1/(2π•4K•4kHz) = 10nF From the Typical Performance Charac- teristics load step curves, the 2.5V output and 3.3V output are stable with RZ = 4KΩ and CC = 10nF. For 1.8V to 0.85V output, the values RZ = 2KΩ and CC = 10nF are recommended. |
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