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SP7663 Datasheet(PDF) 7 Page - Sipex Corporation |
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SP7663 Datasheet(HTML) 7 Page - Sipex Corporation |
7 / 16 page Mar12-07 RevD SP7663 Evaluation Board Manual ©2007 Sipex Corp. Page 7 of 16 Step by step design procedures: Choose fs/10 fco = 60Khz 600Khz/10 fco = = Calculate fp_LC, the double pole frequency of the filter ) C L ( 2 1 fp_LC ⋅ = π 13Khz 99 . 12 ) 100 5 . 1 2π 1 fp_LC ≈ = ⋅ ⋅ = Khz uF uH Calculate fz_ESR the ESR zero frequency Cout Cesr 2π 1 fz_ESR ⋅ ⋅ = hz Khz µF m π ESR fz Κ ≈ = ⋅ ⋅ = 400 88 . 397 ) 100 ( ) 4 ( 2 1 _ Select R1 component value such that 50kΩ ≤ R1 ≤ 100kΩ R1 = 68.1kΩ, 1% Calculate R2 base on the desired VOUT 1 8 . 1 2 − = V Vout R R Ω ≈ Ω = − Ω = K K V V K R 5 . 21 79 . 21 1 8 . 3 . 3 1 . 68 2 Select the ratio of RZ2 / R1 gain for the desired gain bandwidth ⋅ ⋅ = LC fp fco Vin pp Vramp R RZ _ max _ _ 1 2 Ω = ⋅ ⋅ = K KHz KHz V V R RZ 2 . 23 13 60 5 . 13 1 1 2 Note: Loop Compensation component calculations discussed in this section are further elaborated in the application note #ANP16, “Loop Compensation of Voltage-Mode Buck Converters”. These calculations shown here can be quickly iterated with the Type III Loop Compensation Calculator on the web at: www.sipex.com/files/Application-Notes/TypeIIICalculator.xls |
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