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SAA7197T Datasheet(PDF) 3 Page - NXP Semiconductors |
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SAA7197T Datasheet(HTML) 3 Page - NXP Semiconductors |
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3 / 16 page  August 1996 3 Philips Semiconductors Product specification Clock Generator Circuit for desktop video systems (CGC) SAA7197 BLOCK DIAGRAM Fig.1 Block diagram. handbook, full pagewidth 11 SAA7197 VCO FREQUENCY DIVIDER 1 : 2 FREQUENCY DIVIDER 1 : 2 DELAY LOOP FILTER PHASE DETECTOR PRE-FILTER AND PULSE SHAPER POWER-ON RESET LFCO CE MS 1 V DDD1 V DDD2 V DDA 517 8 7 10 20 15 14 LLCA LLCB LLC2A LLC2B CREF RESN 12 4 V SSA V SSD 6, 9, 13, 18 3 PORD MEH461 2 19 LFCO2 LFCOSEL 16 MS = LOW FUNCTION DESCRIPTION The SAA7197 generates all clock signals required for a digital TV system suitable for the SAA719x family consisting of an 8-bit analog-to-digital converter (ADC8), digital video multistandard decoder, square pixel (DMSD-SQP), digital video colour space converter (DCSC) and optional extensions. The SAA7197 completes a system for Desktop Video applications in conjunction with memory controllers. The input signal LFCO is a digital-to-analog converted signal provided by the DMDS-SQPs horizontal PLL. It is the multiple of the line frequency: 7.38 MHz = 472 × fH in 50 Hz systems 6.14 MHz = 360 × fH in 60 Hz systems LFCO2 (TTL-compatible signal from an external reference source) can be applied to pin 19 (LFCOSEL = HIGH). The input signal LFCO or LFCO2 is multiplied by factors 2 or 4 in the PLL (including phase detector, loop filter, VCO and frequency divider) and output on LLCA (pin7), LLCB (pin 10), LLC2A (pin 14) and LLC2B (pin 20). The rectangular output signals have 50% duty factor. Outputs with equal frequency may be connected together externally. The clock outputs go HIGH during power-on reset (and chip enable) to ensure that no output clock signals are available the PLL has locked-on. Mode select MS The LFCO input signal is directly connected to the VCO at MS = HIGH. The circuit operates as an oscillator and frequency divider. This function is not tested. |
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