July 1991

8

Philips Semiconductors

Product specification

Audio Digital Input Circuit (ADIC)

SAA7274

• Outputs ODCL, OWSY, OBSY and OSDA are enabled via a 3-state mode with a HIGH level on input IDOEN.

• IPHEN input selects dual or single edge detection of the input signal IBIFA in the phase detector. A low level selects

the single-edge detection mode.

• Out-of-lock signal (OLOC). This output is continuously LOW or random HIGH/LOW if the PLL is out-of-lock, or no block

preambles and present in the biphase input signal IBIFA. It is continuously HIGH if the PLL is in lock.

• User data/pre-emphasis output signal (OSDU). After receiving a category code of mode 0 from a non-compact disc

source this signal outputs the pre-emphasis bit of the channel status bits in the biphase input signal. If the category

code of mode 0 is from a compact disc source then the user data bits from the subcode channel including the CRC

check on the 96 preceding Q bits are output.

• User clock/copy bit output signal (OSCU). After receiving a category code of mode 0 from a non-compact disc source

then the copy bit of the channel status bits in the biphase input signal is output. If the category code of mode 0 is from

a compact disc source then 10 clock pulses for the ‘user data’ are output.

• Pre-emphasis level output signal (OPRE), which indicates the value of the pre-emphasis bit of the channel status bits

after receiving the two-channel audio format in the biphase input signal (IBIFA).

• Control data bits output signal (OCDB), which contains the 4 control bits of each word of the biphase input signal.

• The inputs ITEST1 and ITEST2 are used for device tests at the factory only, for normal operation they have to be

Clock oscillator

The clock oscillator of the circuit can be formed by connecting a crystal or a ceramic resonator between the oscillator

input and output pins.

The circuit can also be driven by an external signal source applied to the oscillator input. The oscillator output is buffered

and available at pin OSCL. The internal circuitry is driven via an inverter, which is connected to the output OSCL. This

allows all the output signals (especially ODCL, OWSY and OBSY) to change their state after a pulse from OSCL,

independent of the capacitive load of the OSCL pin. All output signals of the circuit are triggered on the positive transition

of the OSCL signal.

Application note

If the capacitive load is higher than specified in AC CHARACTERISTICS, a buffer circuit can be used. A suitable device

is the PC74HC126 (3-state quad buffer/line driver). The input IDOEN to the SAA7274 must be made HIGH and the

original 3-state enable signal must be connected to the OE inputs of the PC74HC126 (pins 1, 4, 10 and 13). Because

the capacitive load of the SAA7274 is very low, the loss of speed is limited.