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SAA7346H Datasheet(PDF) 9 Page - NXP Semiconductors |
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SAA7346H Datasheet(HTML) 9 Page - NXP Semiconductors |
9 / 24 page July 1994 9 Philips Semiconductors Preliminary specification Shock absorbing RAM addresser SAA7346 Table 3 Internal status signals. Table 4 FIFO length as a function of CONFIG, Lm and Lm1. STATUS DESCRIPTION Lm and Lm1 The two Most Significant Bits (MSB) of the FIFO. These can be used to display the FIFO length or correct the subcode time information. The FIFO length is shown in Table 4. FRM_ER Framing error flag is set when: 1. The microcontroller did not accept the previous subcode flag on time. When this occurs the NSF flag will be set together with FRM_ER. 2. The S_NSF generated signal does not coincide with the NSF signal generated by the decoder. When this occurs there has been a FIFO overflow in the decoder or a jump. Framing error flag is reset when status register is read. NSF New subcode frame is set when an absolute sync is recovered from the CFLG input. Reset when status register is read. If the NSF is still set at the next occurrence of a subcode frame, FRM_ER will be set indicating that the microcontroller has lost a frame. Full Full is set when the FIFO is full. When the flag is set the microcontroller must jump back to the previous track. Reset when status register is read. Empty Empty is set when the FIFO is emptied during hold or shock modes. DRAM writing should resume immediately unless echo is set in the command register. If set, writing can only resume when PFB or flush are set in the command register. The latter will cause a discontinuity in music. Note when set there is a complete word left in the FIFO giving the SAA7346 controller time to switch to fill mode. SSD Set shock detect is set when SAA7346 detects a shock. Fill Fill is set when writing data to the DRAM or by setting the command register flags PFB or flush. Reset internally when full or SSD are set. CONFIG Lm Lm1 FIFO LENGTH (s) 0 0 0 0.00 to 0.19 0 0 1 0.19 to 0.39 0 1 0 0.39 to 0.58 0 1 1 0.58 to 0.78 1 0 0 0.00 to 0.75 1 0 1 0.75 to 1.50 1 1 0 1.50 to 2.25 1 1 1 2.25 to 2.97 Fig.7 Microcontroller READ timing. handbook, full pagewidth B7 B6 B5 B4 B3 B2 B1 B0 SICL SILD SIDA MGB434 |
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