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SAA7374GP Datasheet(PDF) 8 Page - NXP Semiconductors |
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SAA7374GP Datasheet(HTML) 8 Page - NXP Semiconductors |
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8 / 60 page  1998 Feb 26 8 Philips Semiconductors Product specification Low voltage digital servo processor and Compact Disc decoder (CD7LV) SAA7374 7 FUNCTIONAL DESCRIPTION 7.1 Decoder part 7.1.1 PRINCIPLE OPERATIONAL MODES OF THE DECODER The decoding part can operate at different disc speeds, from single-speed (n = 1) up to double-speed (n = 2). The factor ‘n’ is called the overspeed factor. A simplified data flow through the decoder part is illustrated in Fig.6. 7.1.2 DECODING SPEED AND CRYSTAL FREQUENCY The SAA7374 is a multi-speed decoding device, with an internal phase-locked loop (PLL) clock multiplier. Depending on the crystal frequency used and the internal clock settings (selectable via register B), the playback speeds shown in Table 1 are possible, where ‘n’ is the overspeed factor. An internal clock multiplier is present, controlled by SELPLL, and should only be used if an 8.4672 MHz crystal, ceramic resonator or external clock is present. 7.1.3 LOCK-TO-DISC MODE For high speed CD-ROM applications, the SAA7374 has a special mode, the lock-to-disc mode. This allows Constant Angular Velocity (CAV) disc playback with varying input data rates from the inside-to-outside of the disc. In the lock-to-disc mode, the FIFO is blocked and the decoder will adjust its output data rate to the disc speed. Hence, the frequency of the I2S-bus (WCLK and SCLK) clocks are dependent on the disc speed. In the lock-to-disc mode there is a limit on the maximum variation in disc speed that the SAA7374 will follow. Disc speeds must always be within 25 to 100% range of their nominal value. The lock-to-disc mode is enabled/disabled by register E. 7.1.4 STANDBY MODES The SAA7374 may be placed in two standby modes selected by register B (it should be noted that the device core is still active) Standby 1: “CD-STOP” mode. Most I/O functions are switched off. Standby 2: “CD-PAUSE” mode. Audio output features are switched off, but the motor loop, the motor output and the subcode interfaces remain active. This is also called a “Hot Pause”. In the standby modes the various pins will have the following values; MOTO1 and MOTO2: put in high-impedance, PWM mode (standby 1 and reset, operating in standby 2). Put in high-impedance, PDM mode (standby 1 and reset, operating in standby 2). SCL, SDA, SILD and RAB: no interaction. Normal operation continues. SCLK, WCLK, DATA, EF, CL11 and DOBM: 3-state in both standby modes. Normal operation continues after reset. CRIN, CROUT, CL16 and CL4: no interaction. Normal operation continues. V1, V2, V3, V4, V5, CFLG and C2FAIL: no interaction. Normal operation continues. Table 1 Playback speeds Note 1. The CL11 output is always a 5.6448 MHz clock if a 16.9344 MHz external clock is used. REGISTER B SELPLL CRYSTAL FREQUENCY (MHz) CL11 FREQUENCY (MHz)(1) 33.8688 16.9344 8.4672 00xx 0 n = 1 −− 11.2896 00xx 1 −− n = 1 11.2896 01xx 0 − n=1 − 5.6448 10xx 0 n = 2 −− 11.2896 10xx 1 −− n = 2 11.2896 11xx 0 − n=2 − 5.6448 |
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