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SAA7381 Datasheet(PDF) 2 Page - NXP Semiconductors |
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SAA7381 Datasheet(HTML) 2 Page - NXP Semiconductors |
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2 / 108 page  1997 Aug 12 2 Philips Semiconductors Objective specification ATAPI CD-R block decoder SAA7381 CONTENTS 1 FEATURES 2 GENERAL DESCRIPTION 2.1 Memory mapped control registers 2.2 Error correction features 2.3 Host interface features 2.4 Buffer memory organisation 2.5 Subcode handling features 2.6 Multimedia output audio control features 3 QUICK REFERENCE DATA 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING 6.1 Detailed description of pin functions 7 FUNCTIONAL DESCRIPTION 7.1 Memory field description 7.1.1 DVD-ROM memory field information 7.2 CD input control registers 7.2.1 Registers associated with data in process 7.3 Multimedia output interface 7.3.1 Subcode input block 7.3.2 Subcode mode transmit control register 7.3.3 General description of the multimedia output interface 7.3.4 IEC 958/EBU output 7.3.5 Memory-to-memory block copy function 7.4 Interrupt registers 7.4.1 Interrupt 1 7.4.2 Interrupt 2 7.4.3 UART interrupt 7.5 Host interface 7.5.1 Introduction 7.5.2 Description of the host interface block 7.5.3 Description of the host interface registers 7.5.4 Transfer counter 7.5.5 Packet size store 7.5.6 Sequencer status 7.5.7 Host interface DMA special bits 7.5.8 Automatic block pointer reload programming 7.5.9 DMA transfer programming of the host interface 7.5.10 Generic interface operation 7.5.11 DMA transfers in generic mode 7.5.12 Normal DMA mode 7.5.13 Burst DMA mode using multiplexed bus configuration 7.6 Microcontroller interface 7.6.1 Kernel based firmware 7.6.2 16-bit registers automatic read and write 7.7 8051 CPU and memory management functions 7.7.1 Sub-CPU bus access timing 7.7.2 Buffer memory organisation 7.7.3 Subpage 7.8 External memory interface 7.8.1 DRAM interface configuration register 7.9 UART for communication with CD engine 7.9.1 UART basic engine interface 7.10 Clock generation control 7.10.1 Crystal oscillator 7.10.2 Sub-CPU clock control register 7.10.3 SAA7381 system clock control registers 8 LIMITING VALUES 9 THERMAL CHARACTERISTICS 10 CHARACTERISTICS 11 TIMING CHARACTERISTICS 11.1 External memory interface timing 11.2 Host interface timing 11.2.1 Host interface ATAPI PIO and DMA timing 11.2.2 ATA bus timing 11.2.3 Ultra DMA operation and timing 11.2.4 Ultra DMA read/write timing 11.3 Sub-CPU interface timing 11.4 UART timing 12 APPENDIX A 13 APPLICATION INFORMATION 14 PACKAGE OUTLINE 15 SOLDERING 15.1 Introduction 15.2 Reflow soldering 15.3 Wave soldering 15.4 Repairing soldered joints 16 DEFINITIONS 17 LIFE SUPPORT APPLICATIONS |
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