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SAA7385GP Datasheet(PDF) 6 Page - NXP Semiconductors |
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SAA7385GP Datasheet(HTML) 6 Page - NXP Semiconductors |
6 / 64 page 1996 Jun 19 6 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (SEQUOIA) SAA7385 RAS 11 O S4 DRAM row address section; active LOW CAS 12 O S4 DRAM column address selection; active LOW DWR 13 O S4 DRAM write; active LOW DOE 14 O S4 DRAM output enable; active LOW VSS2 15 −− ground 2 DD0 16 I/O 4 mA, Schmitt, PD25 DRAM data bus; bit DD0 DD1 17 I/O 4 mA, Schmitt, PD25 DRAM data bus; bit DD1 DD2 18 I/O 4 mA, Schmitt, PD25 DRAM data bus; bit DD2 DD3 19 I/O 4 mA, Schmitt, PD25 DRAM data bus; bit DD3 VDD2 20 −− power supply 2 DD4 21 I/O 4 mA, Schmitt, PD25 DRAM data bus; bit DD4 DD5 22 I/O 4 mA, Schmitt, PD25 DRAM data bus; bit DD5 DD6 23 I/O 4 mA, Schmitt, PD25 DRAM data bus; bit DD6 DD7 24 I/O 4 mA, Schmitt, PD25 DRAM data bus; bit DD7 VSS3 25 −− ground 3 LED 26 O 24 mA, CMOS test panel LED; active LOW; WTGCTL(4) TRAYSW 27 I Schmitt, PU25 active LOW when tray is in EJECT 28 I Schmitt, PU25 opens tray; active LOW LQDATA 29 O 2 mA serial data to DAC LWCLK 30 O 2 mA word strobe to DAC VSS4 31 −− ground 4 SCLK 32 O 2 mA data serial clock VSS5 33 −− ground 5 SYSRES 34 O 2 mA, PU25 system reset; OR of POR, SCSIRST and watch-dog timer CFLAG 35 I Schmitt, PU400 C1 and C2 status CPR 36 O 2 mA S2B interface ready to accept data; active LOW SPR 37 I Schmitt S2B interface ready to send data; active LOW SKIPFWD 38 I Schmitt, PU25 skip forwards; active LOW; RDSW(3) SKIPBACK 39 I Schmitt, PU25 skip backwards; active LOW; RDSW(2) SCSICLK 40 I standard SCSI interface clock VDD3 41 −− power supply 3 AD0 42 I/O S4, Schmitt microcontroller multiplexed data bus; bit AD0 AD1 43 I/O S4, Schmitt microcontroller multiplexed data bus; bit AD1 AD2 44 I/O S4, Schmitt microcontroller multiplexed data bus; bit AD2 AD3 45 I/O S4, Schmitt microcontroller multiplexed data bus; bit AD3 AD4 46 I/O S4, Schmitt microcontroller multiplexed data bus; bit AD4 AD5 47 I/O S4, Schmitt microcontroller multiplexed data bus; bit AD5 AD6 48 I/O S4, Schmitt microcontroller multiplexed data bus; bit AD6 AD7 49 I/O S4, Schmitt microcontroller multiplexed data bus; bit AD7 VSS6 50 −− ground 6 LA0 51 O CMOS S2, PU25 EPROM latched lower address; bit LA0 SYMBOL PIN I/O PAD DESCRIPTION |
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