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SCN68652 Datasheet(PDF) 7 Page - NXP Semiconductors |
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SCN68652 Datasheet(HTML) 7 Page - NXP Semiconductors |
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7 / 22 page  Philips Semiconductors Product specification SCN2652/SCN68652 Multi-protocol communications controller (MPCC) 1995 May 01 7 FUNCTIONAL DESCRIPTION The MPCC can be functionally partitioned into receiver logic, transmitter logic, registers that can be read or loaded by the processor, and data bus control circuitry. The register bit formats are shown in Figure 3 while the receiver and transmitter data paths are depicted in Figures 4 and 3. RECEIVER OPERATION General After initializing the parameter control registers (PCSAR and PCR), the RxE input must be set high to enable the receiver data path. The serial data on the RxSI is synchronized and shifted into an 8-bit Control Character Shift Register (CCSR) on the rising edge of RxC. A comparison between CCSR contents and the FLAG (BOP) or SYNC (BCP) character is made until a match is found. At that time, the S/F output is asserted for one RxC time and the 16-bit Holding Shift Register (HSR) is enabled. The receiver then operates as described below. BOP Operation A flowchart of receiver operation in BOP mode appears in Figure 6. Zero deletion (after five ones are received) is implemented on the received serial data so that a data character will not be interpreted as a FLAG, ABORT, or GA. Bits following the FLAG are shifted through the CCSR, HSR, and into the Receiver Shift Register (RxSR). A character will be assembled in the RxSR and transferred to the RDSRL for presentation to the processor. At that time the RxDA output will be asserted and the processor must take the character no later than one RxC time after the next character is assembled in the RxSR. If not, an overrun (RDSR11 = 1) will occur and succeeding characters will be lost. The first character following the FLAG is the secondary station address. If the MPCC is a secondary station (PCSAR12 = 1), the contents of RxSR are compared with the address stored in PCSARL. A match indicates the forthcoming message is intended for the station; the RxA output is asserted, the character is loaded into RDSRL, RxDA is asserted and the Receive Start of Message bit (RSOM) is set. No match indicates that another station is being addressed and the receiver searches for the next FLAG. If the MPCC is a primary station, (PCSAR12 = 0), no secondary address check is made; RxA is asserted and RSOM is set once the first non-FLAG character has been loaded into RDSRL and RxDA has been asserted. Extended address field can be supported by software if PCSAR12 = 0. When the 8 bits following the address character have been loaded into RDSRL and RxDA has been asserted, RSOM will be cleared. The processor should read this 8-bit character and interpret it as the Control field. Received serial data that follows is read and interpreted as the information field by the processor. It will be assembled into character lengths as specified by PCR8–10. As before, RxDA is asserted each time a character has been transferred into RDSRL and is cleared when RDSRL is read by the processor. RDSRH should only be read when RxSA is asserted. This occurs on a zero to one transition of any bit in RDSRH except for RSOM. RxSA and all bits in RDSRH except RSOM are cleared when RDSRH is read. The processor should check RDSR9–15 each time RxSA is asserted. If RDSR9 is set, then RDSR12–15 should be examined. Receiver character length may be changed dynamically in response to RxDA: read the character in RxDB and write the new character length into RxCL. The character length will be changed on the next receiver character boundary. A received residual (short) character will be transferred into RxDB after the previous character in RxDB has been read, i.e. there will not be an overrun. In general the last two characters are protected from overrun. The CRC–CCITT, if specified by PCSAR8–10, is accumulated in RxCRC on each character following the FLAG. When the closing FLAG is detected in the CCSR, the received CRC is in the 16-bit HSR. At that time, the Receive End of Message bit (REOM) will be set; RxSA and RxDA will be asserted. The processor should read the last data character in RDSRL and the receiver status in RDSR9–15. If RDSR15 = 1, there has been a transmission error; the accumulated CRC–CCITT is incorrect. If RDSR12–14 ≠ 0, last data character is not of prescribed length. Neither the received CRC nor closing FLAG are presented to the processor. The processor may drop RxE or leave it active at the end of the received message. RxBCP Operation The operation of the receiver in BCP mode is shown in Figure 7. The receiver initially searches for two successive SYNC characters, of length specified by PCR8–10, that match the contents of PCSARL. The next non-SYNC character or next SYNC character, if stripping is not specified (PCSAR13 = 0), causes RxA to be asserted and enables the receiver data path. Once enabled, all characters are assembled in RxSR and loaded into RDSRL. RxDA is active when a character is available in RDSRL. RxSA is active on a 0 to 1 transition of any bit in RDSRH. The signals are cleared when RDSRl or RDSRH are read respectively. If CRC–16 error control is specified by PCSAR8–10, the processor must determine the last character received prior to the CRC field. When that character is loaded into RDSRL and RxDA is asserted, the received CRC will be in CCSR and HSRL. To check for a transmission error, the processor must read the receiver status (RDSRH) and examine RDSR15. This bit will be set for one character time if an error free message has been received. If RDSR15 = 0, the CRC–16 is in error. The state of RDSR15 in BCP CRC mode does not set RxSA. Note that this bit should be examined only at the end of a message. The accumulated CRC will include all characters starting with the first non-SYNC character if PCSAR13 = 1, or the character after the opening two SYNCs if PCSAR13 = 0. This necessitates external CRC generation/checking when supporting IBM’s BISYNC. This can be accomplished using the Philips Semiconductors SCN2653 Polynomial Generator/Checker. See Typical Applications. If VRC has been selected for error control, parity (odd or even) is regenerated on each character and checked when the parity bit is received. A discrepancy causes RDSR15 to be set and RxSA to be asserted. This must be sensed by the processor. The received parity bit is stripped before the character is presented to the processor. When the processor has read the last character of the message, it should drop RxE which disables the receiver logic and initializes all receiver registers and timing. |
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