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SCN2681AC1N28 Datasheet(PDF) 7 Page - NXP Semiconductors |
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SCN2681AC1N28 Datasheet(HTML) 7 Page - NXP Semiconductors |
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7 / 30 page  Philips Semiconductors Product specification SCN2681 Dual asynchronous receiver/transmitter (DUART) 1998 Sep 04 7 BLOCK DIAGRAM 8 D0–D7 RDN WRN CEN A0–A3 RESET INTRN X1/CLK X2 4 BUS BUFFER OPERATION CONTROL ADDRESS DECODE R/W CONTROL INTERRUPT CONTROL IMR ISR TIMING BAUD RATE GENERATOR CLOCK SELECTORS COUNTER/ TIMER XTAL OSC CSRA CSRB ACR CTUR CHANNEL A TRANSMIT HOLDING REG TRANSMIT SHIFT REGISTER RECEIVE HOLDING REG (3) RECEIVE SHIFT REGISTER MRA1, 2 CRA SRA INPUT PORT CHANGE OF STATE DETECTORS (4) OUTPUT PORT FUNCTION SELECT LOGIC OPCR TxDA RxDA IP0-IP6 OP0-OP7 VCC GND CHANNEL B (AS ABOVE) IPCR ACR OPR CTLR RxDB TxDB 8 7 SD00085 Figure 2. Block Diagram BLOCK DIAGRAM The SCN2681 DUART consists of the following eight major sections: data bus buffer, operation control, interrupt control, timing, communications Channels A and B, input port and output port. Refer to the block diagram. Data Bus Buffer The data bus buffer provides the interface between the external and internal data buses. It is controlled by the operation control block to allow read and write operations to take place between the controlling CPU and the DUART. Operation Control The operation control logic receives operation commands from the CPU and generates appropriate signals to internal sections to control device operation. It contains address decoding and read and write circuits to permit communications with the microprocessor via the data bus buffer. Interrupt Control A single active-Low interrupt output (INTRN) is provided which is activated upon the occurrence of any of eight internal events. Associated with the interrupt system are the Interrupt Mask Register |
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