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TMS470R1VC002 Datasheet(PDF) 8 Page - Texas Instruments |
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TMS470R1VC002 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 42 page TMS470R1VC002 16/32-BIT RISC ROM MICROCONTROLLER SPNS072B – NOVEMBER 2001 – REVISED OCTOBER 2002 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443 Terminal Functions (Continued) † I = input, O = output, PWR = power, GND = ground, REF = reference voltage, NC = no connect ‡ All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high. § IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.) TERMINAL TYPE†‡ INTERNAL PULLUP/ PULLDOWN§ DESCRIPTION NAME NO. SYSTEM MODULE (SYS) CLKOUT 59 3.3-V I/O IPD Bidirectional pin. CLKOUT can be programmed as a GIO pin or the output of SYSCLK, ICLK, or MCLK. Note: If this pin is to be used as an input, it is recommended that an external pulldown be used. PORRST 21 3.3-V I IPD Input master chip power-up reset. External VCC monitor circuitry must assert a power- on reset. RST 10 3.3-V I/O IPU Bidirectional reset. The internal circuitry can assert a reset, and an external system reset can assert a device reset. On this pin, the output buffer is implemented as an open drain (drives low only). To ensure an external reset is not arbitrarily generated, TI recommends that an external pullup resistor be connected to this pin. WATCHDOG/REAL-TIME INTERRUPT (WD/RTI) AWD 50 3.3-V I/O IPD Analog watchdog reset. The AWD pin provides a system reset if the WD KEY is not written in time by the system, providing an external RC network circuit is connected. For more details on the external RC network circuit, see the TMS470R1x System Module Reference Guide (literature number SPNU189). TEST/DEBUG (T/D) TCK 54 3.3-V I IPD Test clock. TCK controls the test hardware (JTAG). TDI 52 3.3-V I IPU Test data in. TDI inputs serial data to the test instruction register, test data register, and programmable test address (JTAG). TDO 53 3.3-V O IPD Test data out. TDO outputs serial data from the test instruction register, test data register, identification register, and programmable test address (JTAG). TEST 27 3.3-V I IPD Test enable. Reserved for internal use only. For proper operation, this pin must be connected to ground. TMS 84 3.3-V I IPU Serial input for controlling the state of the CPU TAP controller (JTAG) TMS2 85 3.3-V I IPU Serial input for controlling the second TAP. For proper operation, this pin must be connected to VCC or not connected. TRST 26 3.3-V I IPD Test hardware reset to TAP1 and TAP2. IEEE Standard 1149-1 (JTAG) Boundary- Scan Logic For proper device operation, the TRST pin must be externally pulled down with a 10-k Ω resistor. SUPPLY VOLTAGE CORE (1.8 V) VCC 9 1.8-V PWR Core logic supply voltage 40 66 87 SUPPLY VOLTAGE DIGITAL I/O (3.3 V) VCCIO 12 3.3-V PWR Digital I/O supply voltage 58 |
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