Philips Semiconductors

Product specification

SCN2661/SCN68661

Enhanced programmable communications

interface (EPCI)

1994 Apr 27

10

Table 5.

Mode Register 1 (MR1)

MR17

MR16

MR15

MR14

MR13

MR12

MR11

MR10

Sync/Async

Parity Type

Parity Control

Character Length

Mode and Baud Rate Factor

Async: Stop bit length

00 = invalid

01 = 1 stop bit

10 = 1 1/2 stop bits

11 = 2 stop bits

0 = Odd

1 = Even

0 = Disabled

1 = Enabled

00 = 5 bits

01 = 6 bits

10 = 7 bits

11 = 8 bits

00 = Synchronous 1X rate

01 = Asynchronous 1X rate

10 = Asynchronous 16X rate

11 = Asynchronous 64X rate

Sync:

Number of

SYN char

0 = Double SYN

1 = Single SYN

Sync:

Transparency

control

0 = Normal

1 = Transparent

NOTE: Baud rate factor in asynchronous applies only if external clock is selected. Factor is 16X if internal clock is selected. Mode must be

selected (MR11, MR10) in any case.

Table 6.

Mode Register 2 (MR2)

MR27 – MR24

MR23 – MR20

TxC

RxC

Pin 9

Pin 25

TxC

RxC

Pin 9

Pin 25

Mode

Baud Rate

Selection

0000

0001

0010

0011

0100

0101

0110

0111

E

E

I

I

E

E

I

I

E

I

E

I

E

I

E

I

TxC

TxC

1X

1X

TxC

TxC

16X

16X

RxC

1X

RxC

1X

RxC

16X

RxC

16X

1000

1001

1010

1011

1100

1101

1110

1111

E

E

I

I

E

E

I

I

E

I

E

I

E

I

E

I

XSYNC*

TxC

XSYNC*

1X

XSYNC*

TXC

XSYNC*

16X

RXC/TxC

BKDET

RxC

BKDET

RxC/TxC

BKDET

RxC

BKDET

sync

async

sync

async

sync

async

sync

async

See baud rates

in Table 1.

NOTES:

*

When pin 9 is programmed as XSYNC input, SYN1, SYN1–SYN2, and DLE–SYN1 detection is disabled.

E = External clock

I

= Internal clock (BRG)

1X and 16X are clock outputs.

Table 7.

Command Register (CR)

CR7

CR6

CR5

CR4

CR3

CR2

CR1

CR0

Operating Mode

Request

to Send

Reset Error

Sync/Async

Receive

Control

(RxEN)

Data Terminal

Ready

Transmit

Control

(TxEN)

00 = Normal operation

01 = Async:

Automatic

Echo mode

Sync: SYN and/or DLE

stripping mode

10 = Local loopback

11 = Remote loopback

0 = Force RTS

Output High

one clock

time after

TxSR

serialization

1 = Force RTS

output Low

0 = Normal

1 = Reset error

flags in

status reg.

(FE,OE,PE/

DLE detect.)

Async:

Force Break

0 = Normal

1 = Force

break

Sync

Send DLE

0 = Normal

1 = Send DLE

0 = Disable

1 = Enable

Not applicable

in

0 = Force DTR

output High

1 = Force DTR

output Low

0 = Disable

1 = Enable