Philips Semiconductors

Product specification

SCN2661/SCN68661

Enhanced programmable communications

interface (EPCI)

1994 Apr 27

4

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNIT

SYMBOL

PARAMETER

TEST CONDITIONS

Min

Typ

Max

UNIT

Pulse width

Reset

Chip enable

1000

250

ns

ns

Setup and hold time

Address setup

Address hold

R/W control setup

R/W control hold

Data setup for write

Data hold for write

RX data setup

RX data hold

10

10

10

10

150

10

300

350

ns

ns

ns

ns

ns

ns

ns

ns

Data delay time for read

Data bus floating time for read

CE to CE delay

600

200

100

ns

ns

ns

Input clock frequency

Baud rate generator (2661A, B)

Baud rate generator (2661C)

TxC or RxC

1.0

1.0

dc

4.9152

5.0688

4.9202

5.0738

1.0

MHz

MHz

MHz

Clock width

Baud rate High (2661A, B)

Baud rate High (2661C)

Baud rate Low (2661A, B)

Baud rate Low (2661C)

TxC or RxC High

TxC or RxC Low

75

70

75

70

480

480

ns

ns

ns

ns

ns

ns

TxD delay from falling edge of TxC

Skew between TxD changing and falling edge

0

650

ns

ns

NOTES:

1. Over recommended free-air operating temperature range and supply voltage range unless otherwise specified. For conditions shown as MIN

or MAX, use the appropriate value specified under recommended operating conditions.

0.8V and 2.0V for outputs. Input levels swing between 0.4V and 2.4V, with a transition time of

≤ 20ns maximum.

3. Typical values are at +25

°C, typical supply voltages and typical processing parameters.

4. Parameter applies when internal transmitter clock is used.

7. See AC load conditions.

BLOCK DIAGRAM

The EPCI consists of six major sections. These are the transmitter,

receiver, timing, operation control, modern control and SYN/DLE

control. These sections communicate with each other via an

internal data bus and an internal control bus. The internal data bus

interfaces to the microprocessor data bus via a data bus buffer.

Operation Control

This functional block stores configuration and operation commands

from the CPU and generates appropriate signals to various internal

sections to control the overall device operation. It contains read and

write circuits to permit communications with the microprocessor via

the data bus and contains mode registers 1 and 2, the command

register, and the status register. Details of register addressing and

protocol are presented in the EPCI programming section of this data

sheet.

Timing

The EPCI contains a Baud Rate Generator (BRG) which is

programmable to accept external transmit or receive clocks or to

divide an external clock to perform data communications. The unit

can generate 16 commonly used baud rates, any one of which can

be selected for full-duplex operation. See Table 1.

Receiver

The receiver accepts serial data on the RxD pin, converts this serial

input to parallel format, checks for bits or characters that are unique

to the communication technique and sends an “assembled”

character to the CPU.

Transmitter

The transmitter accepts parallel data from the CPU, converts it to a

serial bit stream, inserts the appropriate characters or bits (based on