STR912FAW44X6 datasheet(45/78 Pages) STMICROELECTRONICS

Part #	STR912FAW44X6

Description	ARM966E-S??16/32-Bit Flash MCU with Ethernet, USB, CAN, AC motor control, 4 timers, ADC, RTC, DMA

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STR91xFA

Memory mapping

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When other AHB bus masters (such as a DMA controller) write to SRAM, their access is never

buffered. Only the CPU can make use of buffered AHB writes.

5.4

Two independent Flash memories

The STR91xFA has two independent Flash memories, the larger primary Flash and the small

secondary Flash. It is possible for the CPU to erase/write to one of these Flash memories while

simultaneously reading from the other.

One or the other of these two Flash memories may reside at the “boot” address position of

0x0000.0000 at power-up or at reset as shown in Figure 9. The default configuration is that the

first sector of primary Flash memory is enabled and residing at the boot position, and the

secondary Flash memory is disabled. This default condition may be optionally changed as

described below.

5.4.1

Default configuration

When the primary Flash resides at boot position, typical CPU initialization firmware would set

the start address and size of the main Flash memory, and go on to enable the secondary Flash,

define it’s start address and size. Most commonly, firmware would place the secondary Flash

start address at the location just after the end of the primary Flash memory. In this case, the

primary Flash is used for code storage, and the smaller secondary flash can be used for data

storage (EEPROM emulation).

5.4.2

Optional configuration

Using the STR91xFA device configuration software tool, or IDE from 3rd party, one can specify

that the smaller secondary Flash memory is at the boot location at reset and the primary Flash

is disabled. The selection of which Flash memory is at the boot location is programmed in a

non-volatile Flash-based configuration bit during JTAG ISP. The boot selection choice will

remain as the default until the bit is erased and re-written by the JTAG interface. The CPU

cannot change this choice for boot Flash, only the JTAG interface has access.

In this case where the secondary Flash defaults to the boot location upon reset, CPU firmware

would typically initialize the Flash memories the following way. The secondary Flash start

address and size is specified, then the primary Flash is enabled and its start address and size

is specified. The primary Flash start address would typically be located just after the final

address location of the secondary Flash. This configuration is particularly well-suited for In-

Application-Programming (IAP). The CPU would boot from the secondary Flash memory,

initialize the system, then check the contents of the primary Flash memory (by checksum or

other means). If the contents of primary Flash is OK, then CPU execution continues from either

Flash memory. If the main Flash contents are incorrect, the CPU, while executing code from the

secondary Flash, can download new data from any STR91xFA communication channel and

program into primary Flash memory. Application code then starts after the new contents of

primary Flash are verified.

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