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AKD4117-B Datasheet(PDF) 4 Page - Asahi Kasei Microsystems |
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AKD4117-B Datasheet(HTML) 4 Page - Asahi Kasei Microsystems |
4 / 20 page ASAHI KASEI [AKD4117-B] <KM077200> 2004/12 - 4 - c. Set-up of Audio format Please set up DIF2-0 bit. LRCK Mode DIF2 bit DIF1 bit DIF0 bit DAUX SDTO I/O 0 0 0 0 24bit, Left justified 16bit, Right justified H/L O 1 0 0 1 24bit, Left justified 18bit, Right justified H/L O 2 0 1 0 24bit, Left justified 20bit, Right justified H/L O 3 0 1 1 24bit, Left justified 24bit, Right justified H/L O 4 1 0 0 24bit, Left justified 24bit, Left justified H/L O Default 5 1 0 1 24bit, I 2S 24bit, I 2S L/H O 6 1 1 0 7 1 1 1 Reserved Table 6. Audio format d. Set-up of CM1 and CM0 The operation mode of PLL is selected by CM1 and CM0. It can be selected by CM1-0 bits. CM1 bit CM0 bit (UNLOCK) PLL X'tal Clock source SDTO source 0 0 - ON ON(Note 1) PLL(RX) RX Default 0 1 - OFF ON X'tal DAUX 0 ON ON PLL(RX) RX 1 0 1 ON ON X'tal DAUX 1 1 - ON ON X'tal DAUX ON: Oscillation (Power-up), OFF: STOP (Power-Down) Note: When the X’tal is not used as clock comparison for fs detection (XTL0, 1= “1,1”), the X’tal is OFF. Table 7. Clock Operation Mode Select |
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