ASAHI KASEI

[AK93C85A/95A/10A]

DAM02E-03

2004/05

- 2 -

General Description

The AK93C85A/95A/10A is a 16384/32768/65536-bit serial CMOS EEPROM divided into

1024/2048/4096 registers of 16 bits each.

The AK93C85A/95A/10A has 4 instructions such as

READ, WRITE, EWEN and EWDS.

Those instructions control the AK93C85A/95A/10A.

The AK93C85A/95A/10A can operate full function under wide operating voltage range from 1.8V to

5.5V.

The charge up circuit is integrated for high voltage generation that is used for write

operation.

A serial interface of AK93C85A/95A/10A, consisting of chip select (CS), serial clock (SK), data-in

(DI) and data-out (DO), can easily be controlled by popular microcontrollers or standard

microprocessors.

AK93C85A/95A/10A takes in the write data from data input pin (DI) to a register

synchronously with rising edge of input pulse of serial clock pin (SK).

And at read operation,

AK93C85A/95A/10A takes out the read data from a register to data output pin (DO) synchronously

with rising edge of SK.

The DO pin is usually in high impedance state.

The DO pin outputs "L" or "H" in case of data

output or Busy/Ready signal output.

Software controlled write protection

When VCC is applied to the part, the part automatically powers up in the ERASE/WRITE Disable

state.

In the ERASE/WRITE disable state, execution of WRITE instruction is disabled.

Before

WRITE instruction is executed, EWEN instruction must be executed.

The ERASE/WRITE enable

state continues until EWDS instruction is executed or VCC is removed from the part.

Execution of a read instruction is independent of both EWEN and EWDS instructions.

Busy/Ready status signal

After a write instruction, the DO output serves as a Busy/Ready status indicator.

After the falling

edge of the CS initiates the self-timed programming cycle, the DO indicates the Busy/Ready status

of the chip if the CS is brought high after a minimum of 250ns (tCS).

DO=logical "0" indicates that

programming is still in progress.

DO=logical "1" indicates that the register at the address specified

in the instruction has been written with the new data pattern contained in the instruction and the part

is ready for a next instruction.

The Busy/Ready status indicator is only valid when CS is active (high).

When CS is low, the DO

output goes into a high impedance state.

The Busy/Ready signal outputs until a start bit (Logic"1") of the next instruction is given to the part.

Type of Products

Model

Memory size

Temp. Range

VCC

Package

AK93C85AM

16K bits

-40°C to +85°C

1.8V to 5.5V

8pin Plastic SSOP

AK93C95AF

32K bits

-40°C to +85°C

1.8V to 5.5V

8pin Plastic SOP

AK93C10AF

64K bits

-40°C to +85°C

1.8V to 5.5V

8pin Plastic SOP