ASAHI KASEI

[AK93C45C/55C/65C]

DAM06E-01

2005/10

- 5 -

WRITE

The write instruction is followed by 16 bits of data to be written into the specified address.

After the

last bit of data is put on the DI pin, the CS pin must be brought low before the next rising edge of the

SK clock.

This falling edge of the CS initiates the self-timed programming cycle.

The DO

indicates the Busy/Ready status of the chip if the CS is brought high after a minimum of ‘tCS’.

DO=logical "0" indicates that programming is still in progress.

DO=logical "1" indicates that the

register at the address specified in the instruction has been written with the new data pattern

contained in the instruction and the part is ready for a next instruction.

WRITE (AK93C45C)

WRITE (AK93C55C)

WRITE (AK93C65C)

Hi-Z

0

tE/W

CS

SK

DI

DO

Start Bit

Op code

tCS

Busy

Ready

AK93C45C output a logic "1" (Ready status),

if previous instruction is WRITE, PAGE WRITE, WRAL.

D0

1

2

3

4

5

8

9

10

11

23

24

25

D1

D2

D14

D15

A0

A1

A4

1

0

1

0

A5

PE

Hi-Z

0

tE/W

CS

SK

DI

DO

Start Bit

Op code

tCS

Busy

Ready

AK93C55C output a logic "1" (Ready status),

if previous instruction is WRITE, PAGE WRITE, WRAL.

D0

1

2

3

4

5

10

11

12

13

25

26

27

D1

D2

D14

D15

A0

A1

A6

1

0

1

0

X: Don't care

X

PE

Hi-Z

0

tE/W

CS

SK

DI

DO

Start Bit

Op code

tCS

Busy

Ready

AK93C65C output a logic "1" (Ready status),

if previous instruction is WRITE, PAGE WRITE, WRAL.

D0

1

2

3

4

5

10

11

12

13

25

26

27

D1

D2

D14

D15

A0

A1

A6

1

0

1

0

A7

PE