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LT1161CSW Datasheet(PDF) 5 Page - Linear Technology |
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LT1161CSW Datasheet(HTML) 5 Page - Linear Technology |
5 / 12 page 5 LT1161 1161fa OPERATIO When the MOSFET gate voltage is less than 1.4V, the timer pin is released. The 14 µA current source then slowly charges the timing capacitor back to 3V where the charge pump again starts to drive the gate pin high. If a fault still exists, such as a short circuit, the sense comparator threshold will again be exceeded and the timer cycle will repeat until the fault is removed (see Figure 2). The LT1161 gate pin has two states, OFF and ON. In the OFF state it is held low, while in the ON state it is pumped to 12V above supply by a self-contained 750kHz charge pump. The OFF state is activated when either the input pin is below 1.4V or the timer pin is below 3V. Conversely, for the ON state to be activated, both the input and timer pins must be above their thresholds. If left open, the input pin is held low by a 75k resistor, while the timer pin is held a diode drop above 3V by a 14 µA pull- up current source. Thus the timer pin automatically re- verts to the ON state, subject to the input also being high. The input has approximately 200mV of hysteresis. The sense pin normally connects to the drain of the power MOSFET, which returns through a low valued drain sense resistor to supply. When the gate is ON and the MOSFET drain current exceeds the level required to generate a 65mV drop across the drain sense resistor, the sense comparator activates a pull-down NPN which rapidly pulls the timer pin below 3V. This in turn causes the timer comparator to override the input pin and activate the gate pin OFF state, thus protecting the power MOSFET. In order for the sense comparator to accurately sense MOSFET drain current, the LT1161 supply pins must be connected directly to the positive side of the drain sense resistors. INPUT 1161 F02 OFF NORMAL OVERCURRENT NORMAL 12V V+ GATE 0V 3V 0V TIMER Figure 2. Timing Diagram APPLICATIONS INFORMATION Input/Supply Sequencing There are no input/supply sequencing requirements for the LT1161. The input may be taken up to 15V with the supply at 0V. When the supply is turned on with an input high, the MOSFET turn-on will be inhibited until the timing capacitor charges to 3V (i.e., for one restart cycle). The two V+ pins (11, 20) must always be connected to each other. Isolating the Inputs Operation in harsh environments may require isolation to prevent ground transients from damaging control logic. The LT1161 easily interfaces to low cost opto-isolators. The network shown in Figure 3 ensures that the input will be pulled above 2V, but not exceed the absolute maximum LT1161 12V TO 48V IN GND 100k 1161 F03 2k LOGIC INPUT 1/4 NEC PS2501-4 LOGIC GND POWER GROUND 51k GND (Each Channel, Refer to Functional Diagram) Figure 3. Isolating the Inputs rating, for supply voltages of 12V to 48V over the entire temperature range. In order to maintain the OFF state, the opto must have less than 20 µA of dark current (leakage) hot. |
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