 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
TDA1315 Datasheet(PDF) 8 Page - NXP Semiconductors |
|
||||||||||||||||||||||||||||||
TDA1315 Datasheet(HTML) 8 Page - NXP Semiconductors |
|
|
8 / 36 page  1995 Jul 17 8 Philips Semiconductors Product specification Digital audio input/output circuit (DAIO) TDA1315H BIPHASE DEMODULATOR In the biphase modulator section, audio and non-audio data are combined into subframes, frames and blocks, and encoded in the biphase-mark format during transmit mode. Although there are always 24 audio bits per sample in a subframe, the number of significant bits can be selected as 16, 18, 20 or 24 via the control register (host mode). AUDIO SECTION In the audio section, the left and right channel audio samples are taken from the demodulated data frames and are output serially in accordance with the I2S-bus format (for details see Chapter “References”[3] pins SD, SCK and WS) when the TDA1315H is in the receive mode (I2S-bus transmitter). The audio output signals are concealed or muted in case certain errors were detected during reception. Mute can be enforced by pin MUTE or via the control register (host mode) and affects, depending on the receive/transmit mode, the I2S-bus or IEC output signals. MUTE is internally synchronized with the audio data. In the transmit mode, there is an additional I2S-bus data input SDAUX made available to accept audio data from, for example, an ADC. This input can be selected either by pin I2SSEL, by the control register or both. The I2S-bus Port can be enabled/disabled by pin I2SOEN, by the control register or both. In the transmit mode, I2S-bus data and timing are supplied by an external source, the TDA1315H then becomes an I2S-bus receiver. In this event, selection of an I2S-bus source determines which signal is to be output at IECO. Although the phase relationship between system clock (SYSCLKI) and I2S timing (SCK) is not critical they must be synchronous with each other, i.e. be derived from the same source. Receive mode The IEC subframe format defines 20 bits for an audio sample, plus 4 auxiliary bits, which can be used to extend the word length. By default, all 24 data bits per sample are output via the I2S-bus Port. This can be changed, however, to 16, 18 or 20 bits via bits 2 and 3 in byte 1 of the control register. The remaining bits will then be zero. The serial audio clock frequency at pin SCK is 64 × fs, i.e. there are 32 clock pulses per audio sample (left or right channel). Apart from detecting the out-of-lock condition of the PLL, received data is checked for the errors listed below. All detected errors will be flagged in the status register and two of them brought out to a pin. Depending on the type of error, different measures are taken. • Validity flag set. This error condition is also output at pin INVALID, simultaneously with the data. The corresponding audio sample is not modified. • Parity check error. A concealment operation is performed on both audio channels (left and right), i.e. the last correctly received stereo sample is output again. • Biphase violation (other than preambles). A concealment operation (hold) is performed on both audio channels (left and right), i.e. the last correctly received stereo sample is output again. • PLL is out-of-lock. This error condition is also output at pin UNLOCK. Both audio output channels (left and right) are set to zero (mute). The error condition is sampled with the HIGH-to-LOW transition of WS, i.e. muting becomes effective when the outputting of a stereo sample begins. When the PLL has locked again, muting is released only after a full block of audio samples has been received, free of errors.The INVALID output will always be set to LOW simultaneously with this muting. In the receive mode it is possible to select the auxiliary I2S-bus data input SDAUX for output at pin SD. However, there will be no suitable system clock available in the event of an open IEC input or a disabled IEC source and output SD will be muted when the TDA1315H is not in lock. Regardless of which source is selected, a MUTE command will always mute the output signal at pin SD and set the INVALID output to LOW regardless of the validity bit value. When mute command is disabled, muting will be released when the outputting of the next stereo sample begins. |
Similar Part No. - TDA1315 |
|
Similar Description - TDA1315 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
