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10 pF

1.4 V

1.4 V

1 V

0.4 V

0 V

–0.4 V

0.4 V

2.4 V

SN65LVDM176

SLLS320D – DECEMBER 1998 – REVISED JULY 2000

Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages

APPLIED VOLTAGES

RESULTING DIFFERENTIAL

RESULTING COMMON-

(V)

INPUT VOLTAGE

MODE INPUT VOLTAGE

(mV)

(V)

1.225

1.175

50

1.2

1.175

1.225

–50

1.2

2.41

2.36

50

2.385

2.36

2.41

–50

2.385

0.05

0

50

0.025

0

0.05

–50

0.025

1.5

0.9

600

1.2

0.9

1.5

–600

1.2

2.4

1.8

600

2.1

1.8

2.4

–600

2.1

0.6

0

600

0.3

0

0.6

–600

0.3

A.

the D.U.T.

Figure 7. Timing Test Circuit and Waveforms

9

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