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TDA1545 Datasheet(PDF) 6 Page - NXP Semiconductors |
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TDA1545 Datasheet(HTML) 6 Page - NXP Semiconductors |
6 / 20 page 1997 Sep 04 6 Philips Semiconductors Preliminary specification Stereo continuous calibration DAC TDA1545A FUNCTIONAL DESCRIPTION The basic operation of the continuous calibration DAC is illustrated in Fig.4. The figure shows the calibration principle (Fig.4a) and operation principle (Fig.4b). During calibration of the MOS current source (Fig.4a) transistor M1 is connected as a diode by applying a reference current. The voltage Vgs on the intrinsic gate-source capacitance Cgs of M1 is then determined by the transistor characteristics. After calibration of the drain current to the reference value IREF, the switch S1 is opened and S2 is switched to the other position (Fig.4b). The gate-to-source voltage Vgs of M1 is not changed because the charge on Cgs is preserved. Therefore the drain current of M1 will still be equal to IREF and this exact duplicate of IREF is now available at the Iout terminal. The 32 current sources and the spare current source of the TDA1545A are continuously calibrated (see Fig.1). The spare current is included to allow for continuous convertor operation. The output of one calibrated source is connected to an 11-bit binary current divider consisting of 2048 transistors. A symmetrical offset decoding principle is incorporated and arranges the bit switching in such a way that the zero-crossing is performed only by the LSB currents. The TDA1545A accepts input serial data formats of 16-bit word length. Left and right data words are time multiplexed. The most significant bit (bit 1) must always be first. The format of data input is shown in Figs 5 and 6. With a LOW level on the word select input (WS) input data is placed in the right input register and with a HIGH level on the WS input data is placed in the left input register. The data in the input registers is simultaneously latched in the output registers which control the bit switches. An internal bias current Ibias (see IBL and IBR in Fig.1) is added to the full-scale output current IFS in order to achieve the maximum dynamic range at the outputs of OP1 and OP2 (see Fig.1). The reference input current IREF controls with gain AFS the current IFS which is a sink current and with gain Abias the Ibias which is a source current (note 1). The current IREF is proportional to VDD so the IFS and Ibias will also be proportional to VDD (note 2) because AFS and Abias are constant. The reference output voltage VREF in Fig.1 is 2⁄3VDD. In this way the maximum dynamic range is achieved over the entire power supply range. The tolerance of the reference input current in Fig.1 depends on the tolerance of the resistors R3, R4 and RREF (note 3). Notes to the functional description 1. IFS =AFS × IREF and Ibias =Abias × IREF 2. 3. V DD1 V DD2 ------------- I FS1 I FS2 ---------- I bias1 I bias2 -------------- == ∆I REF I = REF V DD R3 ∆R3 R4 ∆R4 R REF ∆R REF ++ ++ + --------------------------------------------------------------------------------------------------------- – |
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