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TDA4691T Datasheet(PDF) 9 Page - NXP Semiconductors |
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TDA4691T Datasheet(HTML) 9 Page - NXP Semiconductors |
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9 / 26 page  September 1993 9 Philips Semiconductors Preliminary specification Sync Processor with Clock (SPC) TDA4691 ∆f0/∆V16 VCO sensitivity 4% control range; depending on current at pin 18 − 360 − kHz/V Input of external oscillator (pin 15) V15 pin voltage AC see Fig.4(b) 1 − 3V V15 pin voltage DC dependent on V19 − 5 − V Rint internal resistance see Fig.4(b) − 7 − k Ω Cint internal capacitance see Fig.4(b) − 4 − pF 13.5 MHz buffer (pin 13) V13 clock HIGH level output voltage I13 = −1 mA; V12 = 4.5 V 2.7 − V12 V V13 clock HIGH level output voltage I13 = 0 mA 2.7 − V12 V V13 clock LOW level output voltage I13 = 2 mA; V12 = 5.5 V 0 − 0.8 V tr rise time see Fig.5 − 20 − ns tf fall time see Fig.5 − 20 − ns D13 mark-to-space ratio V13 = 1.5 V 45/55 − 55/45 % CL load capacitance −− 40 pF ∆T 13 jitter on clock output (peak-to-peak value) normal time constant T2; measured between lines 25 and 305 −− 2ns H-output buffer (pin 11) V11 H HIGH level output voltage I11 = −1 mA; V12 = 4.5 V 2.7 − V12 V V11 H HIGH level output voltage I11 = 0 mA 2.7 − V12 V V11 H LOW level output voltage I11 = 2 mA; V12 = 5.5 V 0 − 0.8 V tr rise time see Fig.6 − 25 − ns tf fall time see Fig.6 − 25 − ns t3 time relation pin 13 to 11 see Fig.6 − 25 55 ns t4 time relation pin 13 to 11 see Fig.6 3 −− ns t5 H-pulse width see Fig.6 3.0 3.6 4.2 µs CL load capacitance see Fig.6 −− 40 pF Start of H-pulse (pin 14) I14 current pin 14 −− ±100 µA t61 time delay pulse between pin 20 and 11 see Fig.6 −1.1 −1.3 −1.5 µs t62 time delay pulse between pin 20 and 11 see Fig.6 −0.6 −0.8 −1.0 µs t63 time delay pulse between pin 20 and 11 see Fig.6 3.8 4.0 4.2 µs t64 time delay pulse between pin 20 and 11 see Fig.6 5.0 5.2 5.4 µs V14 (t 61) voltage pin 14 (proportional to V19)0 − 1V SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT |
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