TLK2201AJR

1.0 Gb to 1.6 Gb SMALL FORMFACTOR ETHERNET TRANSCEIVER

SLLS614A − MARCH 2004 − REVISED MAY 2007

4

POST OFFICE BOX 655303

detailed description

data transmission

The TLK2201AJR supports both the defined 10-bit interface (TBI) and a reduced 5-bit interface with DDR

clocking. When MODESEL is low, the TBI mode is selected. When MODESEL is high, the DDR mode is

selected.

In the TBI mode, the transmitter portion registers incoming 10-bit wide data words (8b/10b encoded data,

TD0−TD9) on the rising edge of REFCLK. The REFCLK is also used by the serializer, which multiplies the clock

by a factor of 10, providing a signal that is fed to the shift register. The 8b/10b encoded data is transmitted

sequentially bit 0 through 9 over the differential high-speed I/O channel.

In the DDR mode, the transmitter accepts 5-bit wide 8-b/10-b encoded data on pins TD0−TD4. In this mode data

is aligned to both the rising and falling edges of REFCLK. The data is then formed into a 10-bit wide word and

sent to the serializer. The data is clocked most significant bit first (i.e. the bits 0−4 of the 8-b/10-b encoded data).

transmission latency

The data transmission latency of the TLK2201AJR is defined as the delay from the initial 10-bit word load to

the serial transmission of bit 9. The minimum latency in TBI mode is 19 bit times. The maximum latency in TBI

mode is 20 bit times. The minimum latency in DDR mode is 29 bit times, and maximum latency in DDR mode

is 30 bit times.

10 Bit Code

TXP, TXN

TD(0−9)

REFCLK

Td(Tx latency)

10 Bit Code

b9

Figure 1. Transmitter Latency Full Rate Mode

data reception

The receiver portion of the TLK2201AJR deserializes the differential serial data. The serial data is retimed based

on an interpolated clock generated from the reference clock. The serial data is then aligned to the 10-bit word

boundaries and presented to the protocol controller along with receive byte clocks (RBC0, RBC1).